wb_mux_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: wb_mux_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- wb_mux.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: wb_mux.vhd
-- Version: v1.00a
-- Description: Write Back stage main mux
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              wb_mux.vhd
-------------------------------------------------------------------------------
-- Author:          stassart
-- History:
--   BJS  2005-03-24    - First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity WB_Mux is
  generic(
    C_TARGET         : TARGET_FAMILY_TYPE := VIRTEX4;
    C_FSL_EXCEPTION  : boolean := true;
    C_USE_EXCEPTIONS : boolean := true;
    C_USE_HW_MUL     : boolean := true;
    C_USE_FPU        : boolean := true;     -- Enable FPU?
    C_USE_MMU        : integer := 0;
    C_MMU_TLB_READ   : boolean := false;
    C_PVR            : integer := 2
    );  
  port (
    WB_Sel_DataBus_Read_Data : in boolean;    -- WB mux select DB_Read_Data
    WB_Steered_Read_Data     : in DATA_TYPE;  -- data from byte_doublet_handle from data steering

    WB_Sel_MEM_Res : in boolean;  -- WB mux select result from MEM stage
    WB_MEM_Result  : in DATA_TYPE;

    WB_Sel_MUL_Res : in boolean;  -- WB mux select result from multiplier
    WB_Mul_Result  : in DATA_TYPE;

    WB_Sel_FPU_Res : in boolean;  -- WB mux select result from FPU
    WB_FPU_Result  : in DATA_TYPE;

    WB_Sel_MMU_Res : in boolean;  -- WB mux select result from MMU
    WB_MMU_Result  : in DATA_TYPE;

    WB_Sel_SPR_ESR : in boolean;  -- Select SPR exception status register
    WB_ESR         : in ESR_TYPE;

    WB_Sel_SPR_EAR : in boolean;  -- Select SPR exception address register
    WB_EAR         : in EAR_TYPE;

    WB_Sel_SPR_EDR : in boolean;  -- Select SPR exception data register
    WB_EDR         : in EDR_TYPE;

    WB_Sel_SPR_FSR : in boolean;  -- Select SPR floating point status register
    WB_FSR         : in FSR_TYPE;

    WB_Sel_SPR_PVR : in boolean;  -- Select SPR processor version register
    WB_PVR         : in PVR_TYPE;

    WB_Sel_SPR_BTR : in boolean;  -- Select SPR Branch Target Register
    WB_BTR         : in BTR_TYPE;

    WB_Exception_Taken : in boolean;    -- Exception
    WB_PC              : in DATA_TYPE;  -- PC to write to register file when
                                        -- taking an exception

    WB_Fwd : out DATA_TYPE  -- Write back forwarding data
    );

end entity WB_Mux;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of WB_Mux is


  ----------------------------------------
  -- Component for FPGA target
  ----------------------------------------
  component WB_Mux_Bit is
    generic(
      C_TARGET            : TARGET_FAMILY_TYPE := VIRTEX4;
      C_LUT_SIZE          : natural := 4;
      C_DATA_WIDTH        : natural := 5
    );  
    port(
      Select_Bits         : in  std_logic_vector(0 to (C_DATA_WIDTH - 1) / C_LUT_SIZE);
      Data_Bits           : in  std_logic_vector(0 to C_DATA_WIDTH - 1);
    
      WB_Exception_Taken  : in  std_logic; -- taking an exception
      WB_PC               : in  std_logic;
  
      WB_Fwd              : out std_logic  -- Write back forwarding data
    );
  end component WB_Mux_Bit;
  
  
  ----------------------------------------
  -- Support functions to calculate data amount.
  ----------------------------------------
  
  type Natural_Vector   is array (natural range <>) of natural;
  
  -- Identify the number of sources for each bit in the data word.
  -- (If adding additional sources the Map_Used_Data_Bits, 
  --  Map_Used_Select_Bits and Count_Bus_Bits functions must be updated)
  function Count_Bus_Bits return Natural_Vector is
    variable size : Natural_Vector(DATA_TYPE'range) := (others => 2);
  begin 
    if C_USE_HW_MUL then
      for I in DATA_TYPE'range loop
        size(I) :=  size(I) + 1;
      end loop;
    end if;
    if C_USE_FPU then
      for I in DATA_TYPE'range loop
        size(I) :=  size(I) + 1;
      end loop;
      for I in FSR_TYPE'range loop
        size(I) :=  size(I) + 1;
      end loop;
    end if;
    if C_USE_MMU >= C_MMU_PROTECT then
      if C_MMU_TLB_READ then
        size(0) :=  size(0) + 1;
        for I in 26 to 31 loop
          size(I) :=  size(I) + 1;
        end loop;
      else
        for I in DATA_TYPE'range loop
          size(I) :=  size(I) + 1;
        end loop;
      end if;
    end if;
    if C_USE_EXCEPTIONS then
      for I in ESR_TYPE'range loop
        size(I) :=  size(I) + 1;
      end loop;
      for I in EAR_TYPE'range loop
        size(I) :=  size(I) + 1;
      end loop;
      for I in BTR_TYPE'range loop
        size(I) :=  size(I) + 1;
      end loop;
    end if;
    if C_FSL_EXCEPTION then
      for I in EDR_TYPE'range loop
        size(I) :=  size(I) + 1;
      end loop;
    end if;
    if C_PVR /= 0 then
      for I in PVR_TYPE'range loop
        size(I) :=  size(I) + 1;
      end loop;
    end if;

    return size;
  end function Count_Bus_Bits;
  
  -- Return the maximum number of selectable sources for any data word bit.
  function Max_Bus_Bits(size : Natural_Vector) return natural is
    variable tmp : natural:= 0;
  begin 
    for I in size'range loop
      if( size(I) > tmp ) then 
        tmp := size(I);
      end if;
    end loop;
    
    return tmp;
  end function Max_Bus_Bits;
  
  -- Return the number of inputs per LUT.
  function Get_LUT_Size return natural is
  begin 
    if(C_TARGET = VIRTEX5) then
      return 6;
    else
      return 4;
    end if;
  end function Get_LUT_Size;
  
  
  ----------------------------------------
  -- Evaluate bit structure
  ----------------------------------------
  constant BIT_SIZE     : Natural_Vector := Count_Bus_Bits;
  constant MAX_SOURCES  : natural:= Max_Bus_Bits(BIT_SIZE);
  constant LUT_SIZE     : natural:= Get_LUT_Size;
  constant SELECT_LAST  : natural:= (MAX_SOURCES-1) / LUT_SIZE;
  

  ----------------------------------------
  -- Types for optimizations.  
  ----------------------------------------
  type Data_Vector      is array (natural range <>) of std_logic_vector(0 to MAX_SOURCES - 1);
  type Ctrl_Vector      is array (natural range <>) of std_logic_vector(0 to SELECT_LAST);
  
  
  ----------------------------------------
  -- Support functions to calculate and extract information.
  ----------------------------------------
  function b2std(data : boolean) return std_logic is
  begin
    if data then
      return '1';
    else
      return '0';
    end if;
  end function b2std;
  
  -- Map used data bits to the source vector (per bit).
  -- (If adding additional sources the Map_Used_Data_Bits, 
  --  Map_Used_Select_Bits and Count_Bus_Bits functions must be updated)