barrel_shifter.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: barrel_shifter.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- barrel_shift.vhd
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        barrel_shift.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              barrel_shift.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2001-09-18    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity barrel_shift is
  generic (
    C_DATA_SIZE : natural range 4 to 64 := 32;
    C_TARGET    : TARGET_FAMILY_TYPE
    );  
  port (
    Clk           : in  std_logic;
    Reset         : in  boolean;
    Op1           : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Not_Barrel_Op : in  std_logic;
    Left_Shift    : in  std_logic;
    Arith_Shift   : in  std_logic;
    Shift         : in  std_logic_vector(0 to 5);
    Barrel_Result : out std_logic_vector(0 to C_DATA_SIZE-1)
    );

end entity barrel_shift;

library unisim;
use unisim.vcomponents.all;

architecture IMP of barrel_shift is

  signal op1_reverse : std_logic_vector(0 to C_DATA_SIZE-1);

  signal A : std_logic_vector(0 to C_DATA_SIZE-1);
  signal B : std_logic_vector(0 to C_DATA_SIZE-1);
  signal C : std_logic_vector(0 to C_DATA_SIZE-1);
  signal D : std_logic_vector(0 to C_DATA_SIZE-1);
  signal E : std_logic_vector(0 to C_DATA_SIZE-1);

  signal C1         : std_logic_vector(0 to C_DATA_SIZE-1);
  signal C2         : std_logic_vector(0 to C_DATA_SIZE-1);
  signal D1         : std_logic_vector(0 to C_DATA_SIZE-1);
  signal D2         : std_logic_vector(0 to C_DATA_SIZE-1);
  signal Last_Mux_1 : std_logic_vector(0 to C_DATA_SIZE-1);
  signal Last_Mux_2 : std_logic_vector(0 to C_DATA_SIZE-1);

  signal void_bit   : std_logic;
  signal void_bit2  : std_logic_vector(0 to 1);
  signal void_bit3  : std_logic_vector(0 to 2);
  signal void_bit4  : std_logic_vector(0 to 3);
  signal void_bit8  : std_logic_vector(0 to 7);
  signal void_bit12 : std_logic_vector(0 to 11);
  signal void_bit16 : std_logic_vector(0 to 15);

  signal left_shift_i : std_logic;
  
begin  -- architecture IMP

  void_bit <= op1(0) when (Arith_Shift = '1') and (Left_Shift = '0') else '0';

  void_bit2  <= void_bit & void_bit;
  void_bit3  <= void_bit & void_bit2;
  void_bit4  <= void_bit2 & void_bit2;
  void_bit8  <= void_bit4 & void_bit4;
  void_bit12 <= void_bit4 & void_bit8;

  -- First Mux

  OP1_Rev : process (Op1) is
    variable t : std_logic_vector(0 to C_DATA_SIZE-1);
  begin  -- process OP1_Rev
    for I in Op1'left to Op1'right loop
      t(I) := Op1(Op1'right - I);
    end loop;  -- I
    op1_reverse <= t;
  end process OP1_Rev;

  left_shift_i <= Left_Shift;

  A <= Op1 when Left_shift_i = '1' else op1_reverse;

  Mux2 : process (A, Shift, void_bit, void_bit2, void_bit3) is
  begin  -- process Mux2
    if (Shift(Shift'right-1 to Shift'right) = "00") then
      B <= A;
    elsif (Shift(Shift'right-1 to Shift'right) = "01") then
      B <= A(A'left+1 to A'right) & void_bit;
    elsif (Shift(Shift'right-1 to Shift'right) = "10") then
      B <= A(A'left+2 to A'right) & void_bit2;
    else
      B <= A(A'left+3 to A'right) & void_bit3;
    end if;
  end process Mux2;

  Only_For_32 : if (C_DATA_SIZE = 32) generate
    
    Mux3_DFF : process (Clk) is
    begin  -- process Mux3_DFF
      if Clk'event and Clk = '1' then  -- rising clock edge
        if Reset then
          C          <= (others => '0');
          void_bit16 <= (others => '0');
        else
          void_bit16 <= void_bit8 & void_bit8;
          if (Shift(Shift'right-3 to Shift'right-2) = "00") then
            C <= B;
          elsif (Shift(Shift'right-3 to Shift'right-2) = "01") then
            C <= B(B'left+4 to B'right) & void_bit4;
          elsif (Shift(Shift'right-3 to Shift'right-2) = "10") then
            C <= B(B'left+8 to B'right) & void_bit8;
          else
            C <= B(B'left+12 to B'right) & void_bit12;
          end if;
        end if;
      end if;
    end process Mux3_DFF;

    Fix_C_Outputs : process (C, void_bit16) is
    begin  -- process Fix_C_Outputs
      C1                        <= C(C'left+16 to C'right) & void_bit16;
      C2(C2'left to C2'left+15) <= void_bit16;
      for I in C2'left+16 to C2'right loop
        C2(I) <= C(47-i);
      end loop;  -- C2'left+16 to C2'right
    end process Fix_C_Outputs;

    Using_FPGA : if (C_TARGET /= RTL) generate
      
      Last_Stage : for I in Barrel_Result'left to Barrel_Result'right generate
        Last_Mux_1_LUT4 : LUT4
          generic map (
            INIT => X"00CA")             -- [bit_vector]
          port map (
            O  => Last_Mux_1(I),         -- [out std_logic]
            I0 => C(I),                  -- [in  std_logic]
            I1 => C1(I),                 -- [in  std_logic]
            I2 => Shift(Shift'right-4),  -- [in  std_logic]
            I3 => Not_Barrel_Op);        -- [in std_logic]

        Last_Mux_2_LUT4 : LUT4
          generic map (
            INIT => X"00CA")             -- [bit_vector]
          port map (
            O  => Last_Mux_2(I),         -- [out std_logic]
            I0 => C(C'right-I),          -- [in  std_logic]
            I1 => C2(I),                 -- [in  std_logic]
            I2 => Shift(Shift'right-4),  -- [in  std_logic]
            I3 => Not_Barrel_Op);        -- [in std_logic]

        Last_Mux_MUXF5 : MUXF5
          port map (
            I0 => Last_Mux_2(I),        -- [in  std_logic]
            I1 => Last_Mux_1(I),        -- [in  std_logic]
            S  => Left_shift_i,         -- [in  std_logic]
            O  => Barrel_Result(I));    -- [out std_logic]

      end generate Last_Stage;
    end generate Using_FPGA;

    Using_RTL : if (C_TARGET = RTL) generate

      Last_Stage : process (C, C1, C2, Shift, Not_Barrel_Op, left_shift_i) is
      begin  -- process Last_Stage
        if (Not_Barrel_Op = '1') then
          Barrel_Result <= (others => '0');
        else
          if (left_shift_i = '1') then
            if (Shift(Shift'right-4) = '1') then
              Barrel_Result <= C1;
            else
              Barrel_Result <= C;
            end if;
          else
            if (Shift(Shift'right-4) = '1') then
              Barrel_Result <= C2;
            else
              for I in 0 to 31 loop
                Barrel_Result(I) <= C(C'right - I);
              end loop;  -- I            end if;
            end if;
          end if;
        end if;
      end process Last_Stage;
    end generate Using_RTL;  
  end generate Only_For_32;
  
end architecture IMP;