prefetch_buffer_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: prefetch_buffer_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- PreFetch_Buffer - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        prefetch_buffer.vhd
-- Version:         v1.00a
-- Description:     Implement the Instruction prefetch buffer
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              prefetch_buffer.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity PreFetch_Buffer_gti is
  generic (
    C_IEXT_BUS_EXCEPTION : boolean;
    C_USE_MMU            : integer
    ); 
  port (
    Clk                      : in  std_logic;
    Reset                    : in  boolean;
    IReady                   : in  std_logic;
    OF_PipeRun               : in  std_logic;
    Jump                     : in  boolean;
    WB_Dbg_exception         : in  boolean;
    IB_Data                  : in  DATA_TYPE;
    IB_Exception             : in  std_logic;
    IF_Instr_Storage_Excep1  : in  std_logic;
    IF_Instr_TLB_Miss_Excep1 : in  std_logic;
    IF_Fetch_In_Progress     : in  boolean;
    of_branch_with_delayslot : in  boolean;
    Valid_Fetch              : out std_logic;
    OF_Valid                 : out boolean;
    Buffer_Full              : out boolean;
    OF_Instr                 : out DATA_TYPE;
    OF_PreDecode             : out std_logic_vector(0 to 10);
    OF_Instr_Exception       : out std_logic;
    OF_Instr_Storage_Excep   : out std_logic;
    OF_Instr_TLB_Miss_Excep  : out std_logic;
    IB_Buffer_En             : out slv_0to3;
    OF_Buffer_Sel            : out slv_0to1
    );

end entity PreFetch_Buffer_gti;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;

architecture IMP of PreFetch_Buffer_gti is

  -----------------------------------------------------------------------------
  -- Functions
  -----------------------------------------------------------------------------

  -- Convert boolean to natural
  function conv_bool_to_int (b : boolean) return natural is
  begin  -- function conv_bool_to_int
    if (b) then
      return 1;
    else
      return 0;
    end if;
  end function conv_bool_to_int;

  component mux4 is
    generic (
      D_Size : natural);
    port (
      A   : in  std_logic_vector(0 to D_Size-1);
      B   : in  std_logic_vector(0 to D_Size-1);
      C   : in  std_logic_vector(0 to D_Size-1);
      D   : in  std_logic_vector(0 to D_Size-1);
      Sel : in  std_logic_vector(0 to 1);
      Res : out std_logic_vector(0 to D_Size-1));
  end component mux4;

  signal jump_load      : boolean;
  signal jump_load_i    : boolean;
  signal jump_load_hold : boolean;

  signal valid_fetch_i : std_logic;

  signal of_Valid_early : std_logic;
  signal of_Valid_I     : std_logic;
  signal buffer_Full_I  : std_logic;

  constant C_Excep_Size : natural := conv_bool_to_int(C_IEXT_BUS_EXCEPTION)       +
                                     conv_bool_to_int(C_USE_MMU >= C_MMU_PROTECT) +
                                     conv_bool_to_int(C_USE_MMU >= C_MMU_PROTECT);
  constant C_PreDecode_Size : natural := 11;
  constant C_Instr_Data_Exp_Size : natural := 32 + C_Excep_Size + C_PreDecode_Size;

  signal if_predecode : std_logic_vector(0 to C_PreDecode_Size-1);

  subtype instr_data_exp_type is std_logic_vector(0 to C_Instr_Data_Exp_Size-1);

  type   ibuffer_array_type is array (0 to 3) of instr_data_exp_type;
  signal ibuffer : ibuffer_array_type;

  signal ib_ibuf_en  : std_logic_vector(ibuffer_array_type'range);
  signal of_ibuf_sel : std_logic_vector(0 to 1);
  signal ex_ibuf_sel : std_logic_vector(0 to 1);
  signal ex_ibuf_en  : std_logic_vector(ibuffer_array_type'range);

  signal ib_ibuf_length       : std_logic_vector(1 to 3);
  signal ib_ibuf_length_2and3 : std_logic;
  signal new_ib_ibuf_length   : std_logic_vector(1 to 3);
  signal ib_ibuf_length_incr  : std_logic_vector(1 to 3);

  signal new_ib_ibuf_length_sum     : std_logic_vector(1 to 3);
  signal new_ib_ibuf_length_carry   : std_logic_vector(1 to 4);
  signal new_ib_ibuf_length_1_carry : std_logic;

  signal ex_branch_with_delayslot_i : boolean;
  signal ex_branch_with_delayslot   : boolean;

  signal if_instr   : instr_data_exp_type;
  signal of_instr_i : instr_data_exp_type;

  signal jump_or_flush : boolean;

begin  -- architecture IMP

  jump_or_flush <= jump or WB_Dbg_exception;
  
  IB_Buffer_En  <= ib_ibuf_en;
  OF_Buffer_Sel <= of_ibuf_sel;

  -----------------------------------------------------------------------------
  -- Predecode certain signals for the OF stage in order to improve frequency
  -----------------------------------------------------------------------------
  if_predecode(IS_STORE_INSTR_POS) <=
    '1' when (IB_Data(RESULT_SEL_POS_TYPE) = LOAD_STORE_DEC) and
             (IB_Data(STORE_POS) = STORE_DEC) else
    '0';
  if_predecode(PreDecode_RD1_Addr) <= IB_Data(REG1_ADDR_POS_TYPE);
  if_predecode(PreDecode_RD2_Addr) <= IB_Data(REG2_ADDR_POS_TYPE);

  Using_All_Exceptions : if (C_IEXT_BUS_EXCEPTION and
                             C_USE_MMU >= C_MMU_PROTECT) generate
    if_instr                <= IB_Data & IB_Exception &
                               IF_Instr_Storage_Excep1 &
                               IF_Instr_TLB_Miss_Excep1 &
                               if_predecode;
    OF_Instr                <= of_instr_i(0 to 31);
    OF_Instr_Exception      <= of_instr_i(32);
    OF_Instr_Storage_Excep  <= of_instr_i(33);
    OF_Instr_TLB_Miss_Excep <= of_instr_i(34);
    OF_PreDecode            <= of_instr_i(35 to 34+C_PreDecode_Size);
  end generate Using_All_Exceptions;

  Using_Two_MMU_Exceptions : if (not C_IEXT_BUS_EXCEPTION and
                                 C_USE_MMU >= C_MMU_PROTECT) generate
    if_instr                <= IB_Data & IF_Instr_Storage_Excep1 &
                               IF_Instr_TLB_Miss_Excep1 & if_predecode;
    OF_Instr                <= of_instr_i(0 to 31);
    OF_Instr_Exception      <= '0';
    OF_Instr_Storage_Excep  <= of_instr_i(32);
    OF_Instr_TLB_Miss_Excep <= of_instr_i(33);
    OF_PreDecode            <= of_instr_i(34 to 33+C_PreDecode_Size);
  end generate Using_Two_MMU_Exceptions;

  Using_Instr_Bus_Exception : if (C_IEXT_BUS_EXCEPTION and
                                  C_USE_MMU < C_MMU_PROTECT) generate
    if_instr                <= IB_Data & IB_Exception & if_predecode;
    OF_Instr                <= of_instr_i(0 to 31);
    OF_Instr_Exception      <= of_instr_i(32);
    OF_Instr_Storage_Excep  <= '0';
    OF_Instr_TLB_Miss_Excep <= '0';
    OF_PreDecode            <= of_instr_i(33 to 32+C_PreDecode_Size);
  end generate Using_Instr_Bus_Exception;

  No_Exception : if (not C_IEXT_BUS_EXCEPTION and
                     C_USE_MMU < C_MMU_PROTECT) generate
    if_instr                <= IB_Data & if_predecode;
    OF_Instr                <= of_instr_i(0 to 31);
    OF_Instr_Exception      <= '0';
    OF_Instr_Storage_Excep  <= '0';
    OF_Instr_TLB_Miss_Excep <= '0';
    OF_PreDecode            <= of_instr_i(32 to 31+C_PreDecode_Size);
  end generate No_Exception;

  -- A restart of the prefetching is done at reset or at a jump
  jump_load <= Reset or jump_or_flush;

  -----------------------------------------------------------------------------
  -- Valid fetch when Iready except during a jump since this will restart
  -- prefetch buffer.
  -----------------------------------------------------------------------------
  valid_fetch_i <= '0' when jump_or_flush else IReady;

  -----------------------------------------------------------------------------
  -- The instruction mux located in OF stage
  -----------------------------------------------------------------------------
  mux4_I1 : mux4
    generic map (
      D_Size => C_Instr_Data_Exp_Size)  -- [natural]
    port map (
      A   => IBuffer(0),   -- [in  std_logic_vector(0 to D_Size-1)]
      B   => IBuffer(1),   -- [in  std_logic_vector(0 to D_Size-1)]
      C   => IBuffer(2),   -- [in  std_logic_vector(0 to D_Size-1)]
      D   => IBuffer(3),   -- [in  std_logic_vector(0 to D_Size-1)]
      Sel => of_ibuf_sel,               -- [in  std_logic_vector(0 to 1)]
      Res => of_instr_i);  -- [out std_logic_vector(0 to D_Size-1)]
  
  -----------------------------------------------------------------------------
  -- The instruction buffers located in the IB stage
  -----------------------------------------------------------------------------
  The_IBuffers : for I in ibuffer_array_type'range generate
    ibuffer_DFF : process (Clk) is
    begin  -- process ibuffer_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset then                   -- synchronous reset (active true)
          IBuffer(I) <= (others => '0');
        else
          if ((ib_ibuf_en(I) = '1') and (valid_fetch_i = '1')) then
            IBuffer(I) <= if_instr;
          end if;
        end if;