mul_unit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

              C_P_REG       => 0,                -- [integer]
              C_OPMODE      => mul_add_p_op,
              C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_USE_PATTERN => "NO_PATDET")      -- [string]
            port map (
              Clk     => Clk,                    -- [in  std_logic]
              Reset_P => '0',                    -- [in  std_logic]
              Reset_M => '0',                    -- [in  std_logic]
              AB_CE   => '1',                    -- [in  std_logic]
              M_CE    => ex_PipeRun_i,           -- [in  std_logic]
              P_CE    => '1',                    -- [in  std_logic]
              OpMode  => mul_add_p_op,           -- [in  std_logic(6 downto 0)]
              A       => ex_b_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
              B       => ex_c_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
              C       => zero48,
              P       => mem_bc_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              P_Copy  => mem_ad_p,
              PCIN    => mem_ad_pout,            -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
              PCOUT   => mem_bc_pout,            -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              DETECT  => open);                  -- [out std_logic]

          dsp_module_I4 : dsp_module
            generic map (
              C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
              C_A_WIDTH     => 18,               -- [natural]
              C_B_WIDTH     => 18,               -- [natural]
              C_P_WIDTH     => 48,               -- [natural]
              C_AB_REG      => 0,                -- [integer]
              C_M_REG       => 1,                -- [integer]
              C_P_REG       => 0,                -- [integer]
              C_OPMODE      => mul_op,
              C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_USE_PATTERN => "NO_PATDET")      -- [string]
            port map (
              Clk     => Clk,                    -- [in  std_logic]
              Reset_M => '0',                    -- [in  std_logic]
              Reset_P => '0',                    -- [in  std_logic]
              AB_CE   => '1',                    -- [in  std_logic]
              M_CE    => ex_PipeRun_i,           -- [in  std_logic]
              P_CE    => '1',                    -- [in  std_logic]
              OpMode  => mul_op,                 -- [in  std_logic(6 downto 0)]
              A       => ex_a_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
              B       => ex_c_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
              C       => zero48,
              P       => mem_ac_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              P_Copy  => zero48,
              PCIN    => zero48,                 -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
              PCOUT   => open,                   -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              DETECT  => open);                  -- [out std_logic]

          mem_ac_bd_concatenate(0 to 30)  <= mem_ac_p(17 to 47);
          mem_ac_bd_concatenate(31 to 47) <= mem_bd_p(14 to 30);

          dsp_module_I5 : dsp_module
            generic map (
              C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
              C_A_WIDTH     => 18,               -- [natural]
              C_B_WIDTH     => 18,               -- [natural]
              C_P_WIDTH     => 48,               -- [natural]
              C_AB_REG      => 0,                -- [integer]
              C_M_REG       => 1,                -- [integer]
              C_P_REG       => 0,                -- [integer]
              C_OPMODE      => p_add_c,
              C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_USE_PATTERN => "NO_PATDET")      -- [string]
            port map (
              Clk     => Clk,                    -- [in  std_logic]
              Reset_M => '0',                    -- [in  std_logic]
              Reset_P => '0',                    -- [in  std_logic]
              AB_CE   => '1',                    -- [in  std_logic]
              M_CE    => '1',                    -- [in  std_logic]
              P_CE    => '1',                    -- [in  std_logic]
              OpMode  => p_add_c,                -- [in  std_logic(6 downto 0)]
              A       => (0 to 17 => '0'),       -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
              B       => (0 to 17 => '0'),       -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
              C       => mem_ac_bd_concatenate,
              P       => mem_upper48_p,          -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              P_Copy  => mem_bc_pout,
              PCIN    => mem_bc_pout,            -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
              PCOUT   => open,                   -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              DETECT  => open);                  -- [out std_logic]

          Lower_Part_Mul32_result : process (Clk) is
          begin  -- process Lower_Part_Mul32_result
            if Clk'event and Clk = '1' then               -- rising clock edge
              if mem_PipeRun_and_not_mul32_op = '1' then  -- synchronous reset (active high)
                wb_mul32_result(15 to 31) <= (others => '0');
              elsif (MEM_PipeRun) then
                wb_mul32_result(15 to 31) <= mem_bd_p(31 to 47);
              end if;
            end if;
          end process Lower_Part_Mul32_result;

          Upper_Part_Mul32_result : process (Clk) is
          begin  -- process Upper_Part_Mul32_result
            if Clk'event and Clk = '1' then               -- rising clock edge
              if mem_PipeRun_and_not_mul32_op = '1' then  -- synchronous reset (active high)
                wb_mul32_result(0 to 14) <= (others => '0');
              elsif (MEM_PipeRun) then
                wb_mul32_result(0 to 14) <= mem_upper48_p(33 to 47);
              end if;
            end if;
          end process Upper_Part_Mul32_result;

          Bits_Mul64_result : process (Clk) is
          begin  -- process Bits_Mul64_result
            if Clk'event and Clk = '1' then               -- rising clock edge
              if mem_PipeRun_and_not_mul64_op = '1' then  -- synchronous reset (active high)
                wb_mul64_result(0 to 31) <= (others => '0');
              elsif (MEM_PipeRun) then
                wb_mul64_result(0 to 31) <= mem_upper48_p(1 to 32);
              end if;
            end if;
          end process Bits_Mul64_result;

          WB_Mul_Result <= wb_mul32_result or wb_mul64_result;
        end generate S3ADSP_MUL64;

        Virtex_MUL64 : if (C_TARGET = VIRTEX4) or (C_TARGET = VIRTEX5) generate

          dsp_module_I2 : dsp_module
            generic map (
              C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
              C_A_WIDTH     => 18,               -- [natural]
              C_B_WIDTH     => 18,               -- [natural]
              C_P_WIDTH     => 48,               -- [natural]
              C_AB_REG      => 0,                -- [integer]
              C_M_REG       => 1,                -- [integer]
              C_P_REG       => 0,                -- [integer]
              C_OPMODE      => mul_add_shift_p_op,
              C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_USE_PATTERN => "NO_PATDET")      -- [string]
            port map (
              Clk     => Clk,                    -- [in  std_logic]
              Reset_P => '0',                    -- [in  std_logic]
              Reset_M => '0',                    -- [in  std_logic]
              AB_CE   => '1',                    -- [in  std_logic]
              M_CE    => ex_piperun_i,           -- [in  std_logic]
              P_CE    => '1',                    -- [in  std_logic]
              OpMode  => mul_add_shift_p_op,     -- [in  std_logic(6 downto 0)]
              A       => ex_a_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
              B       => ex_d_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
              C       => zero48,
              P_Copy  => zero48,
              P       => mem_ad_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              PCIN    => mem_bd_pout,            -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
              PCOUT   => mem_ad_pout,            -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              DETECT  => open);                  -- [out std_logic]

          dsp_module_I3 : dsp_module
            generic map (
              C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
              C_A_WIDTH     => 18,               -- [natural]
              C_B_WIDTH     => 18,               -- [natural]
              C_P_WIDTH     => 48,               -- [natural]
              C_AB_REG      => 0,                -- [integer]
              C_M_REG       => 1,                -- [integer]
              C_P_REG       => 0,                -- [integer]
              C_OPMODE      => mul_add_p_op,
              C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_USE_PATTERN => "NO_PATDET")      -- [string]
            port map (
              Clk     => Clk,                    -- [in  std_logic]
              Reset_P => '0',                    -- [in  std_logic]
              Reset_M => '0',                    -- [in  std_logic]
              AB_CE   => '1',                    -- [in  std_logic]
              M_CE    => ex_PipeRun_i,           -- [in  std_logic]
              P_CE    => '1',                    -- [in  std_logic]
              OpMode  => mul_add_p_op,           -- [in  std_logic(6 downto 0)]
              A       => ex_b_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
              B       => ex_c_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
              C       => zero48,
              P_Copy  => zero48,
              P       => mem_bc_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              PCIN    => mem_ad_pout,            -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
              PCOUT   => mem_bc_pout,            -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              DETECT  => open);                  -- [out std_logic]

          dsp_module_I4 : dsp_module
            generic map (
              C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
              C_A_WIDTH     => 18,      -- [natural]
              C_B_WIDTH     => 18,      -- [natural]
              C_P_WIDTH     => 48,      -- [natural]
              C_AB_REG      => 0,       -- [integer]
              C_M_REG       => 1,       -- [integer]
              C_P_REG       => 1,       -- [integer]
              C_OPMODE      => mul_add_shift_p_op,
              C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_USE_PATTERN => "NO_PATDET")      -- [string]
            port map (
              Clk     => Clk,           -- [in  std_logic]
              Reset_M => '0',           -- [in  std_logic]
              Reset_P => mem_PipeRun_and_not_mul64_op,  -- [in  std_logic]
              AB_CE   => '1',           -- [in  std_logic]
              M_CE    => ex_PipeRun_i,  -- [in  std_logic]
              P_CE    => mem_piperun_i,          -- [in  std_logic]
              OpMode  => mul_add_shift_p_op,     -- [in  std_logic(6 downto 0)]
              A       => ex_a_oper,     -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
              B       => ex_c_oper,     -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
              C       => zero48,
              P_Copy  => zero48,
              P       => wb_ac_p,       -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              PCIN    => mem_bc_pout,   -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
              PCOUT   => open,          -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              DETECT  => open);         -- [out std_logic]


          Lower_Part_Mul32_result : process (Clk) is
          begin  -- process Lower_Part_Mul32_result
            if Clk'event and Clk = '1' then               -- rising clock edge
              if mem_PipeRun_and_not_mul32_op = '1' then  -- synchronous reset (active high)
                wb_mul32_result(15 to 31) <= (others => '0');
              elsif (MEM_PipeRun) then
                wb_mul32_result(15 to 31) <= mem_bd_p(31 to 47);
              end if;
            end if;
          end process Lower_Part_Mul32_result;

          Upper_Part_Mul32_result : process (Clk) is
          begin  -- process Upper_Part_Mul32_result
            if Clk'event and Clk = '1' then               -- rising clock edge
              if mem_PipeRun_and_not_mul32_op = '1' then  -- synchronous reset (active high)
                wb_mul32_result(0 to 14) <= (others => '0');
              elsif (MEM_PipeRun) then
                wb_mul32_result(0 to 14) <= mem_bc_p(33 to 47);
              end if;
            end if;
          end process Upper_Part_Mul32_result;

          LSB_Bits_Mul64_result : process (Clk) is
          begin  -- process LSB_Bits_Mul64_result
            if Clk'event and Clk = '1' then               -- rising clock edge
              if mem_PipeRun_and_not_mul64_op = '1' then  -- synchronous reset (active high)
                wb_mul64_result(30 to 31) <= "00";
              elsif (MEM_PipeRun) then
                wb_mul64_result(30 to 31) <= mem_bc_p(31 to 32);
              end if;
            end if;
          end process LSB_Bits_Mul64_result;

          wb_mul64_result(0 to 29) <= wb_ac_p(18 to 47);

          WB_Mul_Result <= wb_mul32_result or wb_mul64_result;
          
        end generate Virtex_MUL64;
      end generate Doing_mul64;

    end generate Using_DSP48_Architectures;

  end generate Use_HW_MUL;

end IMP;