mul_unit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

                  (0 to 11 => '0') & mem_prod_AD_plus_BC_high_I;
              else                         -- MULH instruction sign extend
                wb_prod_AD_plus_BC_high <=
                  (0 to 11 => mem_prod_AD_plus_BC_high_I(0)) &
                  mem_prod_AD_plus_BC_high_I;
              end if;
            end if;  -- MEM_PipeRun
          end if;
        end process Prod_AD_Plus_BC_high_DFF;

        -- Lower 16 bits BD_l
        wb_mul32_result(DATA_LOWER_HW) <= wb_prod_BD(DATA_LOWER_HW);
        -- Upper 16 bits (BD_u + AD_l + BC_l)
        wb_mul32_result(DATA_UPPER_HW) <= wb_prod_BD_plus_AD_plus_BC(1 to 16);
        
        Sum_WB_Mul64_Result_PROCESS : process (wb_prod_AC, wb_prod_BD_plus_AD_plus_BC_Carry,
                                               wb_prod_AD_plus_BC_high) is
          variable Carry : DATA_TYPE;
        begin  -- process Sum_WB_Mul64_Result
          -- Upper 32 bits (AD_u + BC_u + AC + Carry_LSW)
          Carry     := (others => '0');
          Carry(31) := wb_prod_BD_plus_AD_plus_BC_Carry;
          wb_mul64_result(0 to 31) <= std_logic_vector (signed(wb_prod_AD_plus_BC_high) +
                                                        signed(wb_prod_AC) +
                                                        signed(Carry));
        end process Sum_WB_Mul64_Result_PROCESS;


        WB_Mul_Result <= wb_mul32_result or wb_mul64_result;
        
      end generate Using_Mul64_2;

      No_Mul64_2 : if (not C_USE_MUL64) generate
        ----------------------------------------
        -- Prod_BD_DFF
        -- WB stage
        -- Take bits 4-35 of B*D for the 32-bit result
        ----------------------------------------
        Prod_BD_DFF : process (Clk) is
        begin  -- process Prod_BD_DFF
          if Clk'event and Clk = '1' then  -- rising clock edge
            if mem_PipeRun_and_not_mul_op = '1' then
              wb_prod_BD <= (others => '0');
            elsif (MEM_PipeRun) then
              wb_prod_BD <= mem_prod_BD(MUL_RES_WORD);
            end if;  -- MEM_PipeRun
          end if;
        end process Prod_BD_DFF;

        ----------------------------------------
        -- Prod_BD_Plus_AD_Plus_BC_DFF
        -- WB stage AD+BC
        ----------------------------------------
        Prod_BD_Plus_AD_Plus_BC_DFF : process (Clk) is
        begin  -- process Prod_BD_Plus_AD_Plus_BC_DFF
          if Clk'event and Clk = '1' then  -- rising clock edge
            if mem_PipeRun_and_not_mul_op = '1' then
              wb_prod_BD_plus_AD_plus_BC <= (others => '0');
            elsif (MEM_PipeRun) then
              wb_prod_BD_plus_AD_plus_BC <= mem_prod_BD_plus_AD_plus_BC;
            end if;  -- MEM_PipeRun
          end if;
        end process Prod_BD_Plus_AD_Plus_BC_DFF;

        -- Lower 16 bits BD_l
        WB_Mul_Result(DATA_LOWER_HW) <= wb_prod_BD(DATA_LOWER_HW);

        -- Upper 16 bits (BD_u + AD_l + BC_l)
        WB_Mul_Result(DATA_UPPER_HW) <= wb_prod_BD_plus_AD_plus_BC(1 to 16);
        
      end generate No_Mul64_2;

    end generate Using_MULT18x18_Architecture;

    ---------------------------------------------------------------------------
    -- Implementation using DSP48
    ---------------------------------------------------------------------------
    Using_DSP48_Architectures : if (DSP48_ARCHITECTURE) generate

      -- (A x B + CIN)             Multiply
      constant mul_op             : std_logic_vector(0 to 6) := "0000101";
      -- PCIN + (A x B + CIN)      P cascade multiply add
      constant mul_add_p_op       : std_logic_vector(0 to 6) := "0010101";
      -- Shift(PCIN) + (A x B + CIN)  17-bit shift feedback feedback add add
      constant mul_add_shift_p_op : std_logic_vector(0 to 6) := "1010101";
      -- PCIN) + C                    P cascade and add
      constant p_add_c            : std_logic_vector(0 to 6) := "0001100";

      signal mem_bd_pout   : std_logic_vector(0 to 47);
      signal mem_bd_p      : std_logic_vector(0 to 47);
      signal mem_ad_pout   : std_logic_vector(0 to 47);
      signal mem_ad_p      : std_logic_vector(0 to 47);
      signal wb_ad_pout    : std_logic_vector(0 to 47);
      signal wb_ad_p       : std_logic_vector(0 to 47);
      signal mem_bc_p      : std_logic_vector(0 to 47);
      signal wb_bc_p       : std_logic_vector(0 to 47);
      signal mem_bc_pout   : std_logic_vector(0 to 47);
      signal mem_ac_p      : std_logic_vector(0 to 47);
      signal wb_ac_p       : std_logic_vector(0 to 47);
      signal zero48        : std_logic_vector(0 to 47);
      signal mem_upper48_p : std_logic_vector(0 to 47);

    begin
      zero48    <= (others => '0');
      ex_A_Oper <= ex_sign_A & ex_sign_A & ex_sign_A & ex_Op1(0 to 14);
      ex_B_Oper <= '0' & ex_Op1(15 to 31);
      ex_C_OPER <= ex_sign_C & ex_sign_C & ex_sign_C & ex_Op2(0 to 14);
      ex_D_Oper <= '0' & ex_Op2(15 to 31);

      dsp_module_I1 : dsp_module
        generic map (
          C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          C_A_WIDTH     => 18,               -- [natural]
          C_B_WIDTH     => 18,               -- [natural]
          C_P_WIDTH     => 48,               -- [natural]
          C_AB_REG      => 0,                -- [integer]
          C_M_REG       => 0,                -- [integer]
          C_P_REG       => 1,                -- [integer]
          C_OPMODE      => mul_op,
          C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
          C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
          C_USE_PATTERN => "NO_PATDET")      -- [string]
        port map (
          Clk     => Clk,                    -- [in  std_logic]
          Reset_P => '0',                    -- [in  std_logic]
          Reset_M => '0',                    -- [in  std_logic]
          AB_CE   => '1',                    -- [in  std_logic]
          M_CE    => '1',                    -- [in  std_logic]
          P_CE    => ex_piperun_i,           -- [in  std_logic]
          OpMode  => mul_op,                 -- [in  std_logic(6 downto 0)]
          A       => ex_b_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
          B       => ex_d_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
          C       => zero48,
          P       => mem_bd_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
          P_Copy  => zero48,
          PCIN    => zero48,                 -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
          PCOUT   => mem_bd_pout,            -- [out std_logic_vector(0 to C_P_WIDTH-1)]
          DETECT  => open);                  -- [out std_logic]


      No_MUL64 : if (not C_USE_MUL64) generate

        dsp_module_I2 : dsp_module
          generic map (
            C_TARGET      => C_TARGET,              -- [TARGET_FAMILY_TYPE]
            C_A_WIDTH     => 18,                    -- [natural]
            C_B_WIDTH     => 18,                    -- [natural]
            C_P_WIDTH     => 48,                    -- [natural]
            C_AB_REG      => 0,                     -- [integer]
            C_M_REG       => 1,                     -- [integer]
            C_P_REG       => 1,                     -- [integer]
            C_OPMODE      => mul_add_shift_p_op,
            C_PATTERN     => (others => '1'),       -- [std_logic_vector(0 to 47)] Only for DSP48E
            C_MASK        => (others => '1'),       -- [std_logic_vector(0 to 47)] Only for DSP48E
            C_USE_PATTERN => "NO_PATDET")           -- [string]
          port map (
            Clk     => Clk,                         -- [in  std_logic]
            Reset_P => mem_PipeRun_and_not_mul_op,  -- [in  std_logic]
            Reset_M => '0',                         -- [in  std_logic]
            AB_CE   => '1',                         -- [in  std_logic]
            M_CE    => ex_piperun_i,                -- [in  std_logic]
            P_CE    => '1',                         -- [in  std_logic]
            OpMode  => mul_add_shift_p_op,          -- [in  std_logic(6 downto 0)]
            A       => ex_a_oper,                   -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
            B       => ex_d_oper,                   -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
            C       => zero48,
            P       => wb_ad_p,                     -- [out std_logic_vector(0 to C_P_WIDTH-1)]
            P_Copy  => mem_bd_p,
            PCIN    => mem_bd_pout,                 -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
            PCOUT   => wb_ad_pout,                  -- [out std_logic_vector(0 to C_P_WIDTH-1)]
            DETECT  => open);                       -- [out std_logic]

        dsp_module_I3 : dsp_module
          generic map (
            C_TARGET      => C_TARGET,              -- [TARGET_FAMILY_TYPE]
            C_A_WIDTH     => 18,                    -- [natural]
            C_B_WIDTH     => 18,                    -- [natural]
            C_P_WIDTH     => 48,                    -- [natural]
            C_AB_REG      => 1,                     -- [integer]
            C_M_REG       => 1,                     -- [integer]
            C_P_REG       => 0,                     -- [integer]
            C_OPMODE      => mul_add_p_op,
            C_PATTERN     => (others => '1'),       -- [std_logic_vector(0 to 47)] Only for DSP48E
            C_MASK        => (others => '1'),       -- [std_logic_vector(0 to 47)] Only for DSP48E
            C_USE_PATTERN => "NO_PATDET")           -- [string]
          port map (
            Clk     => Clk,                         -- [in  std_logic]
            Reset_P => '0',                         -- [in  std_logic]
            Reset_M => mem_PipeRun_and_not_mul_op,  -- [in  std_logic]
            AB_CE   => ex_piperun_i,                -- [in  std_logic]
            M_CE    => mem_piperun_i,               -- [in  std_logic]
            P_CE    => '1',                         -- [in  std_logic]
            OpMode  => mul_add_p_op,                -- [in  std_logic(6 downto 0)]
            A       => ex_b_oper,                   -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
            B       => ex_c_oper,                   -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
            C       => zero48,
            P       => wb_bc_p,                     -- [out std_logic_vector(0 to C_P_WIDTH-1)]
            P_Copy  => wb_ad_p,
            PCIN    => wb_ad_pout,                  -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
            PCOUT   => open,                        -- [out std_logic_vector(0 to C_P_WIDTH-1)]
            DETECT  => open);                       -- [out std_logic]

        WB_Mul_Result(0 to 14) <= wb_bc_p(33 to 47);

        Lower_Part_Mul_result : process (Clk) is        begin  -- process Lower_Part_Mul_result
          if Clk'event and Clk = '1' then             -- rising clock edge
            if mem_PipeRun_and_not_mul_op = '1' then  -- synchronous reset (active high)
              WB_Mul_Result(15 to 31) <= (others => '0');
            elsif (MEM_PipeRun) then
              WB_Mul_Result(15 to 31) <= mem_bd_p(31 to 47);
            end if;
          end if;
        end process Lower_Part_Mul_result;
        
      end generate No_MUL64;

      Doing_mul64 : if (C_USE_MUL64) generate

        S3ADSP_MUL64 : if (C_TARGET = SPARTAN3ADSP) generate
          
          signal mem_ac_bd_concatenate : std_logic_vector(0 to 47);
        begin

          dsp_module_I2 : dsp_module
            generic map (
              C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
              C_A_WIDTH     => 18,               -- [natural]
              C_B_WIDTH     => 18,               -- [natural]
              C_P_WIDTH     => 48,               -- [natural]
              C_AB_REG      => 0,                -- [integer]
              C_M_REG       => 1,                -- [integer]
              C_P_REG       => 0,                -- [integer]
              C_OPMODE      => mul_op,
              C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
              C_USE_PATTERN => "NO_PATDET")      -- [string]
            port map (
              Clk     => Clk,                    -- [in  std_logic]
              Reset_P => '0',                    -- [in  std_logic]
              Reset_M => '0',                    -- [in  std_logic]
              AB_CE   => '1',                    -- [in  std_logic]
              M_CE    => ex_piperun_i,           -- [in  std_logic]
              P_CE    => '1',                    -- [in  std_logic]
              OpMode  => mul_op,                 -- [in  std_logic(6 downto 0)]
              A       => ex_a_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
              B       => ex_d_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
              C       => zero48,
              P_Copy  => zero48,
              P       => mem_ad_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              PCIN    => zero48,                 -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
              PCOUT   => mem_ad_pout,            -- [out std_logic_vector(0 to C_P_WIDTH-1)]
              DETECT  => open);                  -- [out std_logic]

          dsp_module_I3 : dsp_module
            generic map (
              C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
              C_A_WIDTH     => 18,               -- [natural]
              C_B_WIDTH     => 18,               -- [natural]
              C_P_WIDTH     => 48,               -- [natural]
              C_AB_REG      => 0,                -- [integer]
              C_M_REG       => 1,                -- [integer]