mul_unit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: mul_unit.vhd,v 1.4 2007/11/09 13:06:27 stefana Exp $
-------------------------------------------------------------------------------
-- mul_unit.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
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--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
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--  **  obligation on the part of Xilinx to provide support.                 **
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--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
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--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        mul_unit.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              mul_unit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.4 $
-- Date:            $Date: 2007/11/09 13:06:27 $
--
-- History:
--   goran  2006-08-23    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-- pragma xilinx_rtl_off
library unisim;
use unisim.vcomponents.all;
-- pragma xilinx_rtl_on

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity mul_unit is
  generic (
    C_TARGET     : TARGET_FAMILY_TYPE;
    C_USE_HW_MUL : boolean := true;     -- Hardware multiplier
    C_USE_MUL64  : boolean := false     -- 64 bit result
    );
  port (
    Clk             : in  std_logic;    -- Clock
    Reset           : in  std_logic;    -- Reset
    EX_Not_Mul_Op   : in  boolean;      -- Disable multiplier
    MEM_Not_Mul_Op  : in  boolean;      -- Disable multiplier
    EX_Mulh_Instr   : in  boolean;      -- Multiply high instruction
    EX_Mulhu_Instr  : in  boolean;      -- Unsigned multiply high instruction
    EX_Mulhsu_Instr : in  boolean;      -- Signed * Unsigned multiply high instruction
    EX_Op1          : in  DATA_TYPE;    -- Execute stage operand 1
    EX_Op2          : in  DATA_TYPE;    -- Execute stage operand 2
    EX_PipeRun      : in  boolean;      -- Move the execute stage
    MEM_PipeRun     : in  boolean;      -- Move the memory stage
    WB_Mul_Result   : out DATA_TYPE     -- WB stage multiplier result
    );
end mul_unit;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of mul_unit is
  component dsp_module is
    generic (
      C_TARGET      : TARGET_FAMILY_TYPE;
      C_A_WIDTH     : natural;
      C_B_WIDTH     : natural;
      C_P_WIDTH     : natural;
      C_AB_REG      : integer;
      C_M_REG       : integer;
      C_P_REG       : integer;
      C_OPMODE      : std_logic_vector(0 to 6)  := (others => '0');
      C_PATTERN     : std_logic_vector(0 to 47) := (others => '1');  --Only for DSP48E
      C_MASK        : std_logic_vector(0 to 47) := (others => '1');  --Only for DSP48E
      C_USE_PATTERN : string                    := "NO_PATDET"
      );
    port (
      Clk     : in  std_logic;
      Reset_P : in  std_logic;
      Reset_M : in  std_logic;
      AB_CE   : in  std_logic;
      M_CE    : in  std_logic;
      P_CE    : in  std_logic;
      OpMode  : in  std_logic_vector(0 to 6);
      A       : in  std_logic_vector(0 to C_A_WIDTH-1);
      B       : in  std_logic_vector(0 to C_B_WIDTH-1);
      C       : in  std_logic_vector(0 to C_P_WIDTH-1);
      P       : out std_logic_vector(0 to C_P_WIDTH-1);
      P_Copy  : in  std_logic_vector(0 to C_P_WIDTH-1);
      PCIN    : in  std_logic_vector(0 to C_P_WIDTH-1);
      PCOUT   : out std_logic_vector(0 to C_P_WIDTH-1);
      DETECT  : out std_logic
      );
  end component dsp_module;
  -----------------------------------------------------------------------------
  -- Internal signal declarations
  -----------------------------------------------------------------------------

begin  -- IMP

  -- No hardware multiplier
  -- Use software multiplier
  No_HW_MUL : if (not C_USE_HW_MUL) generate
    WB_Mul_Result <= (others => '0');
  end generate No_HW_MUL;

  Use_HW_MUL : if (C_USE_HW_MUL) generate

     constant DSP48_ARCHITECTURE : boolean := (C_TARGET = VIRTEX4) or
                                              (C_TARGET = VIRTEX5) or
                                              (C_TARGET = SPARTAN3ADSP);
--      constant DSP48_ARCHITECTURE : boolean := (C_TARGET = VIRTEX4) or
--                                               (C_TARGET = VIRTEX5);

    -- Operands to multiplier AB * CD each one 16-bits + fill
    signal ex_a_oper : MUL_OP_TYPE;
    signal ex_b_oper : MUL_OP_TYPE;
    signal ex_c_oper : MUL_OP_TYPE;
    signal ex_d_oper : MUL_OP_TYPE;

    signal ex_sign_A : std_logic;
    signal ex_sign_C : std_logic;

    -- RTL
    signal mem_prod_BD : MUL_RES_TYPE;
    signal mem_prod_AD : MUL_RES_TYPE;
    signal mem_prod_BC : MUL_RES_TYPE;

    signal mem_prod_AD_plus_BC_I       : std_logic_vector(0 to 16);
    signal mem_prod_BD_plus_AD_plus_BC : std_logic_vector(0 to 16);

    -- Only used for C_MUL64
    signal mem_mulh_instr             : boolean;
    signal mem_mulhu_instr            : boolean;
    signal mem_mul64_instr            : boolean;
    signal mem_prod_AC                : MUL_RES_TYPE;
    signal mem_prod_AD_plus_BC_high_I : std_logic_vector(0 to 19);

    signal wb_prod_BD                 : DATA_TYPE;
    signal wb_prod_BD_plus_AD_plus_BC : std_logic_vector(0 to 16);

    -- Only used for C_MUL64
    signal wb_prod_AC              : DATA_TYPE;
    signal wb_prod_AD_plus_BC_high : DATA_TYPE;

    signal mem_PipeRun_and_not_mul_op   : std_logic;
    signal mem_PipeRun_and_not_mul32_op : std_logic;
    signal mem_PipeRun_and_not_mul64_op : std_logic;
    signal wb_mul32_result              : std_logic_vector(0 to 31);
    signal wb_mul64_result              : std_logic_vector(0 to 31);


    signal ex_PipeRun_i  : std_logic;
    signal mem_PipeRun_i : std_logic;

  begin

    -----------------------------------------------------------------------------
    -- Operand1 = AB
    -- Operand2 = CD
    --
    -- A, B, C, and D are each 16 bits filled to 18 bits
    -- DSP blocks are 18-bit x 18-bit = 36-bit
    --
    --         32-bit multiply:
    --                              AB
    --                            * CD
    --                        --------
    --                             D*B (36-bit result)     mem_prod_BD
    --                           D*A << 16 (36-bit result) mem_prod_AD
    --
    --                         + C*B << 16                 mem_prod_BC
    --                        --------
    --          Lower 16-bits:
    --                             BD (lower 16-bits: 20-35)
    --          Upper 16-bits:
    --                             BD (bits 4-19)
    --                             AD (lower 16-bits: 20-35) -] mem_prod_AD_plus_BC_I
    --                           + BC (lower 16-bits: 20-35) -]
    --
    --                   ----------------------------------------------------
    --
    --         64-bit multiply:
    --                              AB
    --                            * CD
    --                      ----------
    --                             D*B (36-bit result)     mem_prod_BD
    --                           D*A << 16 (36-bit result) mem_prod_AD
    --
    --                           C*B << 16 (36-bit result) mem_prod_BC
    --                       + C*A   << 32 (36-bit result)
    --                      ----------
    --          Lower 16-bits:
    --                             BD (lower 16-bits: 20-35)
    --          Upper 16-bits:
    --                             BD (bits 4-19)
    --                             AD (lower 16-bits: 20-35) -] mem_prod_AD_plus_BC_I
    --                           + BC (lower 16-bits: 20-35) -]
    --          Upper 32-bits:
    --                             BD (bits 0-3)
    --                             AD (bits 0-19)
    --                             BC (bits 0-19)
    --                           + AC (bits 4-35)
    --                         
    -----------------------------------------------------------------------------