fpu_mul.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    dsp_module_I2 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,               -- [natural]
        C_B_WIDTH     => 18,               -- [natural]
        C_P_WIDTH     => 48,               -- [natural]
        C_AB_REG      => 0,                -- [integer]
        C_M_REG       => 1,                -- [integer]
        C_P_REG       => 0,                -- [integer]
        C_OPMODE      => mul_op,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,                    -- [in  std_logic]
        Reset_M => '0',                    -- [in  std_logic]
        Reset_P => '0',                    -- [in  std_logic]
        AB_CE   => '1',                    -- [in  std_logic]
        M_CE    => ex_piperun_i,           -- [in  std_logic]
        P_CE    => '1',                    -- [in  std_logic]
        OpMode  => mul_op,                 -- [in  std_logic(6 downto 0)]
        A       => ex_a_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => ex_d_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P       => mem_ad_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        P_Copy  => (0 to 47 => '0'),
        PCIN    => (0 to 47 => '0'),        -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => mem_ad_pout,            -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);                  -- [out std_logic]

    dsp_module_I3 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,               -- [natural]
        C_B_WIDTH     => 18,               -- [natural]
        C_P_WIDTH     => 48,               -- [natural]
        C_AB_REG      => 0,                -- [integer]
        C_M_REG       => 1,                -- [integer]
        C_P_REG       => 0,                -- [integer]
        C_OPMODE      => mul_add_p_op,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,                    -- [in  std_logic]
        Reset_M => '0',                    -- [in  std_logic]
        Reset_P => '0',                    -- [in  std_logic]
        AB_CE   => '1',                    -- [in  std_logic]
        M_CE    => ex_PipeRun_i,           -- [in  std_logic]
        P_CE    => '1',                    -- [in  std_logic]
        OpMode  => mul_add_p_op,           -- [in  std_logic(6 downto 0)]
        A       => ex_b_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => ex_c_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P       => mem_bc_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        P_Copy  => mem_ad_p,
        PCIN    => mem_ad_pout,            -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => mem_bc_pout,            -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);                  -- [out std_logic]

    dsp_module_I4 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,               -- [natural]
        C_B_WIDTH     => 18,               -- [natural]
        C_P_WIDTH     => 48,               -- [natural]
        C_AB_REG      => 0,                -- [integer]
        C_M_REG       => 1,                -- [integer]
        C_P_REG       => 0,                -- [integer]
        C_OPMODE      => mul_op,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,                    -- [in  std_logic]
        Reset_M => '0',                    -- [in  std_logic]
        Reset_P => '0',
        AB_CE   => '1',                    -- [in  std_logic]
        M_CE    => ex_PipeRun_i,           -- [in  std_logic]
        P_CE    => '1',                    -- [in  std_logic]
        OpMode  => mul_op,                 -- [in  std_logic(6 downto 0)]
        A       => ex_a_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => ex_c_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P       => mem_ac_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        P_Copy  => mem_bc_p,
        PCIN    => (0 to 47 => '0'),        -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => open,                   -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);                  -- [out std_logic]

    mem_ac_bd_concatenate(0 to 30) <= mem_ac_p(17 to 47);
    mem_ac_bd_concatenate(31 to 47) <= mem_bd_p(14 to 30);

    dsp_module_I5 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,               -- [natural]
        C_B_WIDTH     => 18,               -- [natural]
        C_P_WIDTH     => 48,               -- [natural]
        C_AB_REG      => 0,                -- [integer]
        C_M_REG       => 1,                -- [integer]
        C_P_REG       => 1,                -- [integer]
        C_OPMODE      => p_add_c,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,                    -- [in  std_logic]
        Reset_M => '0',                    -- [in  std_logic]
        Reset_P => '0',                    -- [in  std_logic]
        AB_CE   => '1',                    -- [in  std_logic]
        M_CE    => '1',                    -- [in  std_logic]
        P_CE    => '1',                    -- [in  std_logic]
        OpMode  => p_add_c,        -- [in  std_logic(6 downto 0)]
        A       => (0 to 17 => '0'),        -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => (0 to 17 => '0'),              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => mem_ac_bd_concatenate,
        P       => mem_upper48_p,                -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        P_Copy  => mem_bc_pout,
        PCIN    => mem_bc_pout,            -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => open,                   -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);                  -- [out std_logic]

    -- Do a vector OR on the 17 least significant bits since these are
    -- always part of the sticky bit
    Lower_Part_Sticky : process (Clk) is
      variable temp : std_logic;
    begin  -- process Lower_Part_Sticky
      if Clk'event and Clk = '1' then               -- rising clock edge
        if Reset = '1' then  -- synchronous reset (active high)
          lower_res_sticky <= '0';
        else
          temp := '0';
          for I in 31 to 47 loop
           temp := temp or mem_bd_p(I);
          end loop;  -- I
          lower_res_sticky <= temp;
        end if;
      end if;
    end process Lower_Part_Sticky;

--    Mul_result : process (Clk) is
--      variable temp : std_logic;
--    begin  -- process Mul_result
--      if Clk'event and Clk = '1' then   -- rising clock edge
--        if Reset = '1' then             -- synchronous reset (active high)
--          mul_res_5_cmb(0 to 26) <= (others => '0');
--          mem_mul_sticky_bit_5_cmb    <= '0';
--        else
--          -- Need 4 more bits of the result for the complete sticky bit
--          temp := lower_res_sticky;
--          for I in 44 to 47 loop
--            temp := temp or mem_upper48_p(I);
--          end loop;
--          mem_mul_sticky_bit_5_cmb <= temp;
--          -- 12 bits is coming from the 3rd DSP module
--          mul_res_5_cmb(0 to 26) <= mem_upper48_p(17 to 43);
--        end if;
--      end if;
--    end process Mul_result;

    mul_res_5_cmb        <= mem_upper48_p(17 to 43);
    mem_mul_sticky_bit_5_cmb <= lower_res_sticky or mem_upper48_p(44) or mem_upper48_p(45) or mem_upper48_p(46) or mem_upper48_p(47);
    
  end generate Using_S3ADSP;

  Using_MULT18 : if ((C_TARGET /= VIRTEX4) and (C_TARGET /= VIRTEX5) and (C_TARGET/=SPARTAN3ADSP)) generate
--  Using_MULT18 : if ((C_TARGET /= VIRTEX4) and (C_TARGET /= VIRTEX5)) generate

    -----------------------------------------------------------------------------
    -- Internal signal declarations
    -----------------------------------------------------------------------------
    -- Operands to multiplier AB * CD each one 16-bits + fill
    signal ex_a_oper : MUL_OP_TYPE;
    signal ex_b_oper : MUL_OP_TYPE;
    signal ex_c_oper : MUL_OP_TYPE;
    signal ex_d_oper : MUL_OP_TYPE;

    -- Multiplication results
    signal mem_prod_BD_2 : MUL_RES_TYPE;
    signal mem_prod_AD_2 : MUL_RES_TYPE;
    signal mem_prod_BC_2 : MUL_RES_TYPE;
    signal mem_prod_AC_2 : MUL_RES_TYPE;

    signal mem_prod_BD_3 : std_logic_vector(4 to MUL_RES_TYPE'right);
    signal mem_prod_AD_3 : std_logic_vector(12 to MUL_RES_TYPE'right);
    signal mem_prod_BC_3 : std_logic_vector(12 to MUL_RES_TYPE'right);
    signal mem_prod_AC_3 : std_logic_vector(20 to 35);

    signal mem_lower_4_cmb     : std_logic_vector(0 to 15);
    signal mul_4_bd_bc_ad      : std_logic_vector(0 to 25);
    signal mem_lower_sticky_4  : std_logic;
    signal mem_prod_BD_BC_AD_4 : std_logic_vector(0 to 25);
    signal mem_prod_AC_4       : std_logic_vector(20 to 35);

    signal mul_res_5_cmb_i : std_logic_vector(0 to 16);

  begin  -- IMP

    -----------------------------------------------------------------------------
    -- Operand1 = AB
    -- Operand2 = CD
    --
    -- A, B, C, and D are each 16 bits filled to 18 bits
    -- MULT blocks are 18-bit x 18-bit = 36-bit
    --
    --         48-bit multiply:
    --                              AB
    --                            * CD
    --                      ----------
    --                             D*B (36-bit result)     mem_prod_BD_2
    --                           D*A << 16 (36-bit result) mem_prod_AD_2
    --
    --                           C*B << 16 (36-bit result) mem_prod_BC_2
    --                       + C*A   << 32 (36-bit result) mem_prod_AC_2
    --                      ----------
    --          Lower 16-bits:
    --                             BD (lower 16-bits: 20-35)
    --          Middle 16-bits:
    --                             BD (bits 4-19)
    --                             AD (lower 16-bits: 20-35) -] mem_prod_AD_plus_BC_I
    --                           + BC (lower 16-bits: 20-35) -]
    --          Upper 16-bits:
    --                                             (BD bits 0-3 always zero)
    --                             AD (bits 12-19) (0-11 always zero)
    --                             BC (bits 12-19) (0-11 always zero)
    --                           + AC (bits 20-35)
    --
    -- The upper 4 bits of BD are not needed because they are always zero:
    -- Maximum values:
    -- 001111111111111111 * 001111111111111111 = 000011111111111111100000000000000001
    --
    -- The upper 12 bits of AD and BC are not needed because they are always zero:
    -- Maximum values:
    -- 000000000011111111 * 001111111111111111 = 000000000000111111101111111100000001
    --                         
    -----------------------------------------------------------------------------

    -----------------------------------------------------------------------------
    -- Stage 1
    -----------------------------------------------------------------------------
    ex_a_oper <= "00000000001" & EX_MantA_1(9 to 15);
    ex_b_oper <= "00" & EX_MantA_1(16 to 31);