fpu_mul.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    mem_mul_sticky_bit_5_cmb <= not(lower_part_detect) or not(upper_part_detect);
    mul_res_5_cmb            <= mem_result_upper(17 to 43);
  end generate Use_Virtex5;

  Using_Virtex4 : if (C_TARGET = VIRTEX4) generate
    signal ex_a_oper : MUL_OP_TYPE;
    signal ex_b_oper : MUL_OP_TYPE;
    signal ex_c_oper : MUL_OP_TYPE;
    signal ex_d_oper : MUL_OP_TYPE;    

    signal mem_bd_pout  : std_logic_vector(0 to 47);
    signal mem_bd_p     : std_logic_vector(0 to 47);
    signal mem_ad_pout : std_logic_vector(0 to 47);
    signal mem_ad_p    : std_logic_vector(0 to 47);
    signal mem_bc_p    : std_logic_vector(0 to 47);
    signal mem_bc_pout : std_logic_vector(0 to 47);
    signal mem_ac_p     : std_logic_vector(0 to 47);

    signal lower_res_sticky : std_logic;

  begin
    ex_a_oper <= "000000000001" & EX_MantA_1(9 to 14);
    ex_b_oper <= '0' & EX_MantA_1(15 to 31);
    ex_c_oper <= "000000000001" & EX_MantB_1(9 to 14);
    ex_d_oper <= '0' & EX_MantB_1(15 to 31);
      
    dsp_module_I1 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,    -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,          -- [natural]
        C_B_WIDTH     => 18,          -- [natural]
        C_P_WIDTH     => 48,          -- [natural]
        C_AB_REG      => 0,           -- [integer]
        C_M_REG       => 0,           -- [integer]
        C_P_REG       => 1,           -- [integer]
        C_OPMODE      => mul_op,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,               -- [in  std_logic]
        Reset_M => '0',               -- [in  std_logic]
        Reset_P => '0',               -- [in  std_logic]
        AB_CE   => '1',               -- [in  std_logic]
        M_CE    => '1',               -- [in  std_logic]
        P_CE    => ex_piperun_i,      -- [in  std_logic]
        OpMode  => mul_op,            -- [in  std_logic(6 downto 0)]
        A       => ex_b_oper,    -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => ex_d_oper,    -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P_Copy  => zero48,
        P       => mem_bd_p,     -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        PCIN    => zero48,       -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => mem_bd_pout,  -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);             -- [out std_logic]
          

    dsp_module_I2 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,    -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,          -- [natural]
        C_B_WIDTH     => 18,          -- [natural]
        C_P_WIDTH     => 48,          -- [natural]
        C_AB_REG      => 0,           -- [integer]
        C_M_REG       => 1,           -- [integer]
        C_P_REG       => 0,           -- [integer]
        C_OPMODE      => mul_add_shift_p_op,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,               -- [in  std_logic]
        Reset_M => '0',               -- [in  std_logic]
        Reset_P => '0',               -- [in  std_logic]
        AB_CE   => '1',               -- [in  std_logic]
        M_CE    => ex_piperun_i,      -- [in  std_logic]
        P_CE    => '1',               -- [in  std_logic]
        OpMode  => mul_add_shift_p_op,     -- [in  std_logic(6 downto 0)]
        A       => ex_a_oper,     -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => ex_d_oper,     -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P_Copy  => zero48,
        P       => mem_ad_p,      -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        PCIN    => mem_bd_pout,   -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => mem_ad_pout,  -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);             -- [out std_logic]

    dsp_module_I3 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,  -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,        -- [natural]
        C_B_WIDTH     => 18,        -- [natural]
        C_P_WIDTH     => 48,        -- [natural]
        C_AB_REG      => 0,         -- [integer]
        C_M_REG       => 1,         -- [integer]
        C_P_REG       => 0,         -- [integer]
        C_OPMODE      => mul_add_p_op,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,             -- [in  std_logic]
        Reset_M => '0',               -- [in  std_logic]
        Reset_P => '0',             -- [in  std_logic]
        AB_CE   => '1',             -- [in  std_logic]
        M_CE    => ex_PipeRun_i,    -- [in  std_logic]
        P_CE    => '1',             -- [in  std_logic]
        OpMode  => mul_add_p_op,    -- [in  std_logic(6 downto 0)]
        A       => ex_b_oper,  -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => ex_c_oper,  -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P_Copy  => zero48,
        P       => mem_bc_p,   -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        PCIN    => mem_ad_pout,  -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => mem_bc_pout,  -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);             -- [out std_logic]

    dsp_module_I4 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,  -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,        -- [natural]
        C_B_WIDTH     => 18,        -- [natural]
        C_P_WIDTH     => 48,        -- [natural]
        C_AB_REG      => 0,         -- [integer]
        C_M_REG       => 1,         -- [integer]
        C_P_REG       => 1,         -- [integer]
        C_OPMODE      => mul_add_shift_p_op,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,             -- [in  std_logic]
        Reset_M => '0',               -- [in  std_logic]
        Reset_P => '0',
        AB_CE   => '1',             -- [in  std_logic]
        M_CE    => ex_PipeRun_i,    -- [in  std_logic]
        P_CE    => '1',   -- [in  std_logic]
        OpMode  => mul_add_shift_p_op,     -- [in  std_logic(6 downto 0)]
        A       => ex_a_oper,  -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => ex_c_oper,  -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P_Copy  => zero48,
        P       => mem_ac_p,    -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        PCIN    => mem_bc_pout,  -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => open,      -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);             -- [out std_logic]

    -- Do a vector OR on the 17 least significant bits since these are
    -- always part of the sticky bit
    Lower_Part_Sticky : process (Clk) is
      variable temp : std_logic;
    begin  -- process Lower_Part_Sticky
      if Clk'event and Clk = '1' then               -- rising clock edge
        if Reset = '1' then  -- synchronous reset (active high)
          lower_res_sticky <= '0';
        else
          temp := '0';
          for I in 31 to 47 loop
           temp := temp or mem_bd_p(I);
          end loop;  -- I
          lower_res_sticky <= temp;
        end if;
      end if;
    end process Lower_Part_Sticky;

    Mul_result : process (Clk) is
      variable temp : std_logic;
    begin  -- process Mul_result
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset = '1' then             -- synchronous reset (active high)
          mul_res_5_cmb(14 to 26) <= (others => '0');
          mem_mul_sticky_bit_5_cmb    <= '0';
        else
          -- Need 4 more bits of the result for the complete sticky bit
          temp := lower_res_sticky;
          for I in 44 to 47 loop
            temp := temp or mem_bc_p(I);
          end loop;
          mem_mul_sticky_bit_5_cmb <= temp;
          -- 12 bits is coming from the 3rd DSP module
          mul_res_5_cmb(14 to 26) <= mem_bc_p(31 to 43);
        end if;
      end if;
    end process Mul_result;

    -- the 14 other bits is coming directly from the DFF from the 4th DSP module
    mul_res_5_cmb(0 to 13) <= mem_ac_p(34 to 47);
    
  end generate Using_Virtex4;

  Using_S3ADSP : if (C_TARGET=SPARTAN3ADSP) generate
    signal ex_a_oper : MUL_OP_TYPE;
    signal ex_b_oper : MUL_OP_TYPE;
    signal ex_c_oper : MUL_OP_TYPE;
    signal ex_d_oper : MUL_OP_TYPE;    

    signal mem_bd_pout           : std_logic_vector(0 to 47);
    signal mem_bd_p              : std_logic_vector(0 to 47);
    signal mem_ad_pout           : std_logic_vector(0 to 47);
    signal mem_ad_p              : std_logic_vector(0 to 47);
    signal mem_bc_p              : std_logic_vector(0 to 47);
    signal mem_bc_pout           : std_logic_vector(0 to 47);
    signal mem_ac_p              : std_logic_vector(0 to 47);
    signal mem_ac_bd_concatenate : std_logic_vector(0 to 47);
    signal mem_upper48_p : std_logic_vector(0 to 47);

    signal lower_res_sticky : std_logic;

  begin
    ex_a_oper <= "000000000001" & EX_MantA_1(9 to 14);
    ex_b_oper <= '0' & EX_MantA_1(15 to 31);
    ex_c_oper <= "000000000001" & EX_MantB_1(9 to 14);
    ex_d_oper <= '0' & EX_MantB_1(15 to 31);
      
    dsp_module_I1 : dsp_module
      generic map (
        C_TARGET      => C_TARGET,         -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 18,               -- [natural]
        C_B_WIDTH     => 18,               -- [natural]
        C_P_WIDTH     => 48,               -- [natural]
        C_AB_REG      => 0,                -- [integer]
        C_M_REG       => 1,                -- [integer]
        C_P_REG       => 0,                -- [integer]
        C_OPMODE      => mul_op,
        C_PATTERN     => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_MASK        => (others => '1'),  -- [std_logic_vector(0 to 47)] Only for DSP48E
        C_USE_PATTERN => "NO_PATDET")      -- [string]
      port map (
        Clk     => Clk,                    -- [in  std_logic]
        Reset_M => '0',                    -- [in  std_logic]
        Reset_P => '0',                    -- [in  std_logic]
        AB_CE   => '1',                    -- [in  std_logic]
        M_CE    => ex_piperun_i,           -- [in  std_logic]
        P_CE    => '1',                    -- [in  std_logic]
        OpMode  => mul_op,                 -- [in  std_logic(6 downto 0)]
        A       => ex_b_oper,              -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => ex_d_oper,              -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P       => mem_bd_p,               -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        P_Copy  => zero48,
        PCIN    => zero48,                 -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => mem_bd_pout,            -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => open);                  -- [out std_logic]