fpu_mul.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: fpu_mul.vhd,v 1.3 2007/11/09 13:06:27 stefana Exp $
-------------------------------------------------------------------------------
-- fpu_mul_unit.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
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--  **  function and run at speed according to the datasheet                 **
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--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
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--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        fpu_mul_unit.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              fpu_mul_unit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.3 $
-- Date:            $Date: 2007/11/09 13:06:27 $
--
-- History:
--   goran  2006-12-12    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity FPU_MUL is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE
    );
  port (
    Clk               : in  std_logic;  -- Clock
    Reset             : in  std_logic;  -- Reset
    EX_MantA_1        : in  FPU_MANT_TYPE;       -- Operand A mantissa
    EX_MantB_1        : in  FPU_MANT_TYPE;       -- Operand B mantissa
    EX_PipeRun        : in  boolean;    -- Move the execute stage
    MEM_Mul_Res_4     : out FPU_MANT_IGRS_TYPE;  -- FPU mantissa multiplicaiton result
    MEM_Mul_Inc_Exp_4 : out boolean     -- Mul increment exponent
    );
end FPU_MUL;

library unisim;
use unisim.vcomponents.all;

architecture IMP of FPU_MUL is

  component dsp_module is
    generic (
      C_TARGET      : TARGET_FAMILY_TYPE;
      C_A_WIDTH     : natural;
      C_B_WIDTH     : natural;
      C_P_WIDTH     : natural;
      C_AB_REG      : integer;
      C_M_REG       : integer;
      C_P_REG       : integer;
      C_OPMODE      : std_logic_vector(0 to 6)  := (others => '0');
      C_PATTERN     : std_logic_vector(0 to 47) := (others => '1');  --Only for DSP48E
      C_MASK        : std_logic_vector(0 to 47) := (others => '1');  --Only for DSP48E
      C_USE_PATTERN : string                    := "NO_PATDET"
      );
    port (
      Clk     : in  std_logic;
      Reset_M : in  std_logic;
      Reset_P : in  std_logic;
      AB_CE   : in  std_logic;
      M_CE    : in  std_logic;
      P_CE    : in  std_logic;
      OpMode  : in  std_logic_vector(0 to 6);
      A       : in  std_logic_vector(0 to C_A_WIDTH-1);
      B       : in  std_logic_vector(0 to C_B_WIDTH-1);
      C       : in  std_logic_vector(0 to C_P_WIDTH-1);
      P       : out std_logic_vector(0 to C_P_WIDTH-1);
      P_Copy  : in  std_logic_vector(0 to C_P_WIDTH-1);
      PCIN    : in  std_logic_vector(0 to C_P_WIDTH-1);
      PCOUT   : out std_logic_vector(0 to C_P_WIDTH-1);
      DETECT  : out std_logic);
  end component dsp_module;

  -- (A x B + CIN)             Multiply
  constant mul_op             : std_logic_vector(0 to 6) := "0000101";
  -- PCIN + (A x B + CIN)      P cascade multiply add
  constant mul_add_p_op       : std_logic_vector(0 to 6) := "0010101";
  -- Shift(PCIN) + (A x B + CIN)  17-bit shift feedback feedback add add
  constant mul_add_shift_p_op : std_logic_vector(0 to 6) := "1010101";
  -- PCIN) + C                    P cascade and add
  constant p_add_c            : std_logic_vector(0 to 6) := "0001100";

 
  signal ex_PipeRun_i : std_logic;
  signal zero48 : std_logic_vector(0 to 47);

  signal mul_res_5_cmb            : std_logic_vector(0 to 26);
  signal mem_mul_res_5_cmb        : FPU_MANT_IGRS_TYPE;
  signal mem_mul_sticky_bit_5_cmb : std_logic;
  -- Increment exponent?
  signal mem_mul_inc_exp_5_cmb    : boolean;

begin  -- architecture IMP

  zero48 <= (others => '0');
  ex_PipeRun_i <= '1' when EX_PipeRun else '0';
  
  -----------------------------------------------------------------------------
  -- Can be implemented in 2 DSP48E blocks
  -----------------------------------------------------------------------------
  Use_Virtex5 : if (C_TARGET = VIRTEX5) generate
    constant lower_part_mask    : std_logic_vector(0 to 47) := (31 to 47 => '0', others => '1');
    constant lower_part_pattern : std_logic_vector(0 to 47) := (others     => '0');

    constant upper_part_mask    : std_logic_vector(0 to 47) := (44 to 47 => '0', others => '1');
    constant upper_part_pattern : std_logic_vector(0 to 47) := (others     => '0');

    signal mantA_25bit       : std_logic_vector(0 to 24);
    signal mantB_18bit_lower : std_logic_vector(0 to 17);
    signal mantB_18bit_upper : std_logic_vector(0 to 17);

    signal lower_part_detect : std_logic;
    signal upper_part_detect : std_logic;

    signal mem_result_lower : std_logic_vector(0 to 47);
    signal mem_result_upper : std_logic_vector(0 to 47);
    signal mem_pcout_lower : std_logic_vector(0 to 47);

  begin
    mantA_25bit       <= "01" & EX_MantA_1;
    mantB_18bit_lower <= "0" & EX_MantB_1(15 to 31);
    mantB_18bit_upper <= "000000000001" & EX_MantB_1(9 to 14);

    dsp_module_lower : dsp_module
      generic map (
        C_TARGET      => C_TARGET,            -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 25,                  -- [natural]
        C_B_WIDTH     => 18,                  -- [natural]
        C_P_WIDTH     => 48,                  -- [natural]
        C_AB_REG      => 0,                   -- [integer]
        C_M_REG       => 1,                   -- [integer]
        C_P_REG       => 0,                   -- [integer]
        C_OPMODE      => mul_op,
        C_PATTERN     => lower_part_pattern,  --Only for DSP48E
        C_MASK        => lower_part_mask,     --Only for DSP48E
        C_USE_PATTERN => "PATDET")            -- [string]
      port map (
        Clk     => Clk,                       -- [in  std_logic]
        Reset_M => '0',                       -- [in  std_logic]
        Reset_P => '0',                       -- [in  std_logic]
        AB_CE   => '1',                       -- [in  std_logic]
        M_CE    => ex_PipeRun_i,              -- [in  std_logic]
        P_CE    => '1',                       -- [in  std_logic]
        OpMode  => mul_op,                    -- [in  std_logic_vector(0 to 6)]
        A       => mantA_25bit,               -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => mantB_18bit_lower,         -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P       => mem_result_lower,          -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        P_Copy  => (0 to 47 => '0'),
        PCIN    => zero48,                    -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => mem_pcout_lower,           -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        DETECT  => lower_part_detect);        -- [out  std_logic]

    dsp_module_upper : dsp_module
      generic map (
        C_TARGET      => C_TARGET,      -- [TARGET_FAMILY_TYPE]
        C_A_WIDTH     => 25,            -- [natural]
        C_B_WIDTH     => 18,            -- [natural]
        C_P_WIDTH     => 48,            -- [natural]
        C_AB_REG      => 0,             -- [integer]
        C_M_REG       => 1,             -- [integer]
        C_P_REG       => 1,             -- [integer]
        C_OPMODE      => mul_add_shift_p_op,
        C_PATTERN     => upper_part_pattern,  --Only for DSP48E
        C_MASK        => upper_part_mask,     --Only for DSP48E
        C_USE_PATTERN => "PATDET")      -- [string]
      port map (
        Clk     => Clk,                 -- [in  std_logic]
        Reset_M => '0',                 -- [in  std_logic]
        Reset_P => '0',                 -- [in  std_logic]
        AB_CE   => '1',                 -- [in  std_logic]
        M_CE    => ex_PipeRun_i,        -- [in  std_logic]
        P_CE    => '1',                 -- [in  std_logic]
        OpMode  => mul_add_shift_p_op,  -- [in  std_logic(6 downto 0)]
        A       => mantA_25bit,  -- [in  std_logic_vector(0 to C_A_WIDTH-1)]
        B       => mantB_18bit_upper,  -- [in  std_logic_vector(0 to C_B_WIDTH-1)]
        C       => (0 to 47 => '0'),
        P       => mem_result_upper,  -- [out std_logic_vector(0 to C_P_WIDTH-1)]
        P_Copy  => mem_result_lower,
        PCIN    => mem_pcout_lower,  -- [in  std_logic_vector(0 to C_P_WIDTH-1)]
        PCOUT   => open,  -- [out std_logic_vector(0 to C_P_WIDTH-1)]        
        DETECT  => upper_part_detect);  -- [out  std_logic]