data_flow_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      C_USE_MUL64  => C_USE_MUL64        -- [boolean]
    )
    port map (
      Clk             => Clk,              -- [in  std_logic]
      Reset           => Reset,            -- [in  boolean]
      EX_Not_Mul_Op   => EX_Not_Mul_Op,    -- [in  boolean]  
      MEM_Not_Mul_Op  => mem_not_mul_op,   -- [in  boolean]  
      EX_Mulh_Instr   => EX_Mulh_Instr,    -- [in  boolean]  
      EX_Mulhu_Instr  => EX_Mulhu_Instr,   -- [in  boolean]  
      EX_Mulhsu_Instr => EX_Mulhsu_Instr,  -- [in  boolean]  
      EX_Op1          => ex_op1_i,         -- [in  DATA_TYPE]
      EX_Op2          => ex_op2,           -- [in  DATA_TYPE]
      EX_PipeRun      => EX_PipeRun,       -- [in  boolean]
      MEM_PipeRun     => MEM_PipeRun,      -- [in  boolean]
      WB_Mul_Result   => wb_mul_result     -- [out DATA_TYPE]
    );

  ex_bs_num_bits <= ex_op2(BSNUM_POS_TYPE);

  ----------------------------------------
  -- Hardware barrel shifter
  -- Stages:
  -- EX: reverse right, perform 0-3 shift, perform 0,4,8,12 shift
  -- MEM: perform 0,16 shift, reverse right
  ----------------------------------------
  Barrel_Shifter_I : Barrel_Shifter_gti
    generic map (
      C_TARGET     => C_TARGET,            -- [TARGET_FAMILY_TYPE]
      C_USE_BARREL => C_USE_BARREL         -- [boolean]
    )
    port map (
      Clk               => Clk,                -- [in  std_logic]
      Reset             => Reset,              -- [in  boolean]
      EX_Op1            => ex_op1_i,           -- [in  DATA_TYPE]
      -- EX_Not_Barrel_Op  => EX_Not_Barrel_Op,   -- [in  boolean]
      EX_Is_BS_Instr    => EX_Is_BS_Instr,     -- [in  boolean]
      EX_Left_Shift     => EX_Left_Shift,      -- [in  boolean]
      EX_Arith_Shift    => EX_Arith_Shift,     -- [in  boolean]
      EX_BS_Num_Bits    => ex_bs_num_bits,     -- [in  BSNUM_TYPE]
      EX_PipeRun        => EX_PipeRun,         -- [in  boolean]
      MEM_Barrel_Result => mem_barrel_result   -- [out DATA_TYPE]
    );

  ----------------------------------------
  -- Instance "EX_MUX_I"
  -- Main EX stage mux
  -- Stages: 
  -- EX - Mux between ALU and shift or FSL
  ----------------------------------------
  ex_fwd_mux: process(EX_Sel_ALU, EX_Sel_FSL, ex_alu_result_i, FSL_Get_Data,
                      ex_shift_logic_result) is
  begin  -- process ex_fwd_mux
    if (EX_Sel_ALU) then
      ex_fwd <= ex_alu_result_i;
    elsif (EX_Sel_FSL) and (C_FSL_LINKS > 0) then
      ex_fwd <= FSL_Get_Data;
    else
      ex_fwd <= ex_shift_logic_result;
    end if;    
  end process ex_fwd_mux;

  ----------------------------------------
  -- Instance "MEM_MUX_I"
  -- Main MEM stage mux
  -- Stages: 
  -- MEM - Mux between EX_Res, div, barrel
  ----------------------------------------
  enable_mem_barrel_result  <= (others=>'1') when C_USE_BARREL else (others=>'0');
  enable_mem_div_result     <= (others=>'1') when C_USE_DIV    else (others=>'0');
  enable_mem_ex_result      <= (others=>'1') when true         else (others=>'0');

  mem_fwd_mux: process (MEM_Sel_Barrel, enable_mem_barrel_result, mem_barrel_result,
                        MEM_Sel_Div, enable_mem_div_result, mem_Div_Result, 
                        MEM_Sel_MSR, mem_msr_i, 
                        enable_mem_ex_result, mem_ex_result) is
  begin  -- process mem_fwd_mux
    mem_fwd   <=  ( mem_barrel_result and enable_mem_barrel_result ) or
                  ( mem_div_result    and enable_mem_div_result ) or
                  ( mem_ex_result     and enable_mem_ex_result );
    

    if (MEM_Sel_MSR) and (C_FSL_LINKS > 0) then
      -- This is needed when a MSR read instruction follows an FSL instruction
      -- Otherwise the MSR read is unchanged
      -- Need to overwrite the CC, C, and FSL bits
      mem_fwd(MSR_CC_POS)  <= mem_msr_i(MSR_CC_POS);
      mem_fwd(MSR_FSL_POS) <= mem_msr_i(MSR_FSL_POS);
      mem_fwd(MSR_C_POS)   <= mem_msr_i(MSR_C_POS);
    end if;
  end process mem_fwd_mux;

  ----------------------------------------
  -- Instance "WB_MUX_I"
  -- Main WB stage mux
  -- Stages: 
  -- WB - Mux between External load data, Mem_Res, Mul, Div, FPU
  ----------------------------------------
  WB_Mux_I : WB_Mux
    generic map (
      C_TARGET         => C_TARGET,
      C_FSL_EXCEPTION  => FSL_EXCEPTION_ON,
      C_USE_EXCEPTIONS => C_USE_EXCEPTIONS,
      C_USE_HW_MUL     => C_USE_HW_MUL,
      C_USE_FPU        => USE_FPU,
      C_USE_MMU        => C_USE_MMU,
      C_MMU_TLB_READ   => C_MMU_TLB_READ,
      C_PVR            => C_PVR
    )
    port map (
      WB_Sel_DataBus_Read_Data => WB_Sel_DataBus_Read_Data,  -- [in  boolean]
      WB_Steered_Read_Data     => wb_steered_read_data,      -- [in  DATA_TYPE]

      WB_Sel_MEM_Res           => WB_Sel_MEM_Res,            -- [in  boolean]
      WB_MEM_Result            => wb_mem_result,             -- [in  DATA_TYPE]

      WB_Sel_MUL_Res           => WB_Sel_MUL_Res,            -- [in  boolean]
      WB_Mul_Result            => wb_mul_result,             -- [in  DATA_TYPE]

      WB_Sel_FPU_Res           => WB_Sel_FPU_Res,            -- [in  boolean]
      WB_FPU_Result            => wb_fpu_result,             -- [in  DATA_TYPE]

      WB_Sel_MMU_Res           => WB_Sel_MMU_Res,            -- [in  boolean]
      WB_MMU_Result            => WB_MMU_Result,             -- [in  DATA_TYPE]

      WB_Sel_SPR_ESR           => WB_Sel_SPR_ESR,            -- [in  boolean]
      WB_ESR                   => wb_esr,                    -- [in  ESR_TYPE]

      WB_Sel_SPR_EAR           => WB_Sel_SPR_EAR,            -- [in  boolean]
      WB_EAR                   => wb_ear,                    -- [in  DATA_TYPE]

      WB_Sel_SPR_EDR           => WB_Sel_SPR_EDR,            -- [in  boolean]
      WB_EDR                   => wb_edr,                    -- [in  DATA_TYPE]
  
      WB_Sel_SPR_FSR           => WB_Sel_SPR_FSR,            -- [in  boolean]
      WB_FSR                   => wb_fsr,                    -- [in  FSR_TYPE]

      WB_Sel_SPR_PVR           => WB_Sel_SPR_PVR,            -- [in  boolean]
      WB_PVR                   => wb_pvr,                    -- [in  PVR_TYPE]

      WB_Sel_SPR_BTR           => WB_Sel_SPR_BTR,            -- [in  boolean]
      WB_BTR                   => wb_btr,                    -- [in  BTR_TYPE]

      WB_Exception_Taken       => wb_exception_taken,        -- [in  boolean]
      WB_PC                    => wb_excep_return_addr,      -- [in  DATA_TYPE]

      WB_Fwd                   => wb_fwd_i                   -- [out DATA_TYPE]
    );

  WB_DataBus_Steered_Read_Data <= wb_steered_read_data;
   
  WB_Fwd <= wb_fwd_i;
  
  ----------------------------------------
  -- Instance "Zero_Detect_I"
  -- Checks if Ra is zero for branch compare instruction
  -- EX_Branch_CMP_Op1 is EX_Op1 without the SPR mux
  -- EX_Op1 is used for the PC for branch instructions
  -- Stages:
  -- EX - check if Ra is zero
  ----------------------------------------
  Zero_Detect_I : Zero_Detect_gti
    generic map (
      C_TARGET => C_TARGET                       -- [TARGET_FAMILY_TYPE]
    )
    port map (
      EX_Op1_CMP_Equal   => EX_Op1_CMP_Equal,    -- [in  boolean]
      EX_Op1_CMP_Equal_n => EX_Op1_CMP_Equal_n,  -- [in  boolean]
      EX_Branch_CMP_Op1  => ex_branch_cmp_op1,   -- [in  DATA_TYPE]
      EX_Op1_Zero        => ex_op1_zero_i        -- [out boolean]
    );

  EX_Op1_Zero <= ex_op1_zero_i;
  
  EX_Op1_Neg <= ex_branch_cmp_op1(QUADLET_SIGN_POS) = '1';

  ----------------------------------------
  -- Instance "Byte_Doublet_Handle_I"
  -- Handles data steering and mirroring
  -- Stages: 
  -- EX - Write data mirroring
  -- WB - Read data steering
  ----------------------------------------
  Byte_Doublet_Handle_I : Byte_Doublet_Handle_gti
    generic map (
      C_TARGET          => C_TARGET            -- [TARGET_FAMILY_TYPE]
      -- pragma xilinx_rtl_off
      ,
      C_U_SET           => C_U_SET             -- [string]
      -- pragma xilinx_rtl_on
    )
    port map (
      Clk   => Clk,                     -- [in  std_logic]
      Reset => Reset,                   -- [in  std_logic]

      EX_PipeRun => EX_PipeRun,         -- [in  boolean]

      EX_Byte_Access    => EX_Byte_Access,     -- [in  boolean]
      EX_Doublet_Access => EX_Doublet_Access,  -- [in  boolean]

      EX_Op1_2LSb => ex_op1_2lsb,       -- [in  slv_0to1]
      EX_Op2_2LSb => ex_op2_2lsb,       -- [in  slv_0to1]

      EX_Op3                       => ex_op3,  -- [in  DATA_TYPE]
      EX_DataBus_Write_Data        => EX_DataBus_Write_Data,  -- [out DATA_TYPE]
      EX_DataBus_Byte_Enable       => EX_DataBus_Byte_Enable,  -- [out DATA_BE_TYPE]
      MEM_DataBus_Write_Data       => MEM_DataBus_Write_Data,  -- [out DATA_TYPE]
      MEM_DataBus_Byte_Enable      => MEM_DataBus_Byte_Enable,  -- [out DATA_BE_TYPE]

      EX_Addr_Low_Bits => EX_Addr_Low_Bits,  -- [out slv_0to1]
      EX_UnAlign_2LSb => ex_unalign_2lsb,  -- [out slv_0to1]
      WB_UnAlign_2LSb => wb_unalign_2lsb,  -- [in  slv_0to1]

      WB_Byte_Access    => WB_Byte_Access,     -- [in  boolean]
      WB_Doublet_Access => WB_Doublet_Access,  -- [in  boolean]

      WB_DataBus_Read_Data => WB_DataBus_Read_Data,  -- [in  DATA_TYPE]
      WB_Steered_Read_Data => WB_steered_read_data   -- [out DATA_TYPE]
      );

  EX_DataBus_Aligned_Addr_2LSb <= ex_unalign_2lsb;
  
  --------------------------------------------------------------------------
  -- Data Flow Logic
  --------------------------------------------------------------------------

  ----------------------------------------
  -- Instance "Data_Flow_Logic_I"
  -- Logic for moving data through stages
  -- Stages: 
  -- EX  - handles 2LSb unaligned bytes and doublet
  -- MEM - Create MEM stage EX result and unaligned 2LSb
  -- WB  - Create WB stage MEM result and unaligned 2LSb
  ----------------------------------------
  Data_Flow_Logic_I : Data_Flow_Logic
    generic map(
      C_MAX_FSL_LINKS  => C_MAX_FSL_LINKS
    )
    port map (
      Clk   => Clk,                     -- [in  std_logic]
      Reset => Reset,                   -- [in  std_logic]

      OF_PipeRun  => OF_PipeRun,        -- [in  boolean]
      EX_PipeRun  => EX_PipeRun,        -- [in  boolean]
      MEM_PipeRun => MEM_PipeRun,       -- [in  boolean]

      EX_Op1 => ex_op1_i,               -- [in  DATA_TYPE]
      EX_Op2 => ex_op2,                 -- [in  DATA_TYPE]

      EX_Op1_2LSb => ex_op1_2lsb,       -- [out slv_0to1]
      EX_Op2_2LSb => ex_op2_2lsb,       -- [out slv_0to1]

      EX_FSL_No          => ex_FSL_No, -- [in  natural range 0 to C_MAX_FSL_LINKS-1]
      WB_FSL_No          => WB_FSL_No, -- [out natural range 0 to C_MAX_FSL_LINKS-1]
    
      EX_Fwd             => ex_fwd,         -- [in  DATA_TYPE]
      MEM_Sel_MEM_Res    => MEM_Sel_MEM_Res,-- [in  boolean]
      EX_Is_BS_Instr     => EX_Is_BS_Instr,
      EX_Is_Div_Instr    => EX_Is_Div_Instr,
      MEM_EX_Result_Load => mem_ex_result_load,
      MEM_EX_Result      => mem_ex_result,  -- [out DATA_TYPE] 

      MEM_Fwd       => mem_fwd,         -- [in  DATA_TYPE]
      WB_MEM_Result => wb_mem_result,   -- [out DATA_TYPE]
      
      EX_Not_Mul_Op  => EX_Not_Mul_Op,   -- [in  boolean]
      MEM_Not_Mul_Op => mem_not_mul_op,  -- [out  boolean]

      EX_Not_FPU_Op  => EX_Not_FPU_Instr,   -- [in  boolean]
      MEM_Not_FPU_Op => mem_not_fpu_instr,  -- [out  boolean]

      EX_UnAlign_2LSb => ex_unalign_2lsb,  -- [in  slv_0to1]
      WB_UnAlign_2LSb => wb_unalign_2lsb,  -- [out slv_0to1]

      WB_Byte_Access    => WB_Byte_Access,     -- [in  boolean]
      WB_Quadlet_Access => WB_Quadlet_Access  -- [in  boolean]
    );

  EX_ALU_Result <= ex_alu_result_i;

  msr_reg_i : msr_reg_gti
    generic map (
      C_RESET_MSR      => C_RESET_MSR,
      C_PVR            => C_PVR,
      C_USE_MMU        => C_USE_MMU,
      C_USE_DIV        => C_USE_DIV,
      C_USE_D_OPB      => USE_D_OPB,
      C_FSL_LINKS      => C_FSL_LINKS,
      C_USE_ICACHE     => USE_ICACHE,
      C_USE_DCACHE     => USE_DCACHE,
      C_USE_EXCEPTIONS => C_USE_EXCEPTIONS
      )
    port map (
      Clk                   => Clk,
      Rst                   => Reset,
      EX_Op1                => ex_op1_i,
      EX_Op2                => ex_op2,
      EX_ALU_Carry          => ex_alu_carry,
      EX_Shift_Carry        => ex_shift_carry,
      EX_FSL_Carry          => ex_fsl_carry,
      EX_FSL_Control_Error  => ex_fsl_control_error,
      MEM_DivideByZero      => mem_dividebyzero,
      OF_PipeRun            => OF_PipeRun,        -- [in  boolean]
      EX_PipeRun            => EX_PipeRun,        -- [in  boolean]
      MEM_PipeRun           => MEM_PipeRun,       -- [in  boolean]
      WB_PipeRun            => WB_PipeRun,        -- [in  boolean]
      EX_MSR_Load_ALU_C     => EX_MSR_Load_ALU_C,
      EX_MSR_Load_Shift_C   => EX_MSR_Load_Shift_C,
      EX_MSR_Load_FSL_C     => ex_fsl_write_carry,
      EX_MSR_Set_IE         => EX_MSR_Set_IE,
      EX_MSR_Set_EE         => EX_MSR_Set_EE,
      EX_MSR_Clear_EIP      => EX_MSR_Clear_EIP,
      EX_MSR_Set_SW_BIP     => EX_MSR_Set_SW_BIP,
      EX_MSR_Clear_BIP      => EX_MSR_Clear_BIP,
      EX_MSR_Clear_VM_UM    => EX_MSR_Clear_VM_UM,
      EX_MTS_MSR            => EX_MTS_MSR,
      EX_MSRCLR             => EX_MSRCLR,
      EX_MSRSET             => EX_MSRSET,
      EX_Restore_WB_MSR     => EX_Restore_WB_MSR,
      MEM_MSR_Load_DZ       => MEM_MSR_Load_DZ,
      WB_MSR_Clear_IE       => WB_