data_flow_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    C_IPLB_BUS_EXCEPTION      : integer;
    C_DPLB_BUS_EXCEPTION      : integer;
    C_OPCODE_0x0_ILLEGAL      : integer;
    C_UNALIGNED_EXCEPTIONS    : integer;
    C_ILL_OPCODE_EXCEPTION    : integer;
    C_IOPB_BUS_EXCEPTION      : integer;
    C_DOPB_BUS_EXCEPTION      : integer;
    C_DIV_ZERO_EXCEPTION      : integer;
    C_FPU_EXCEPTION           : integer;
    C_FSL_EXCEPTION           : integer;
    C_USE_EXTENDED_FSL_INSTR  : integer := 0;
    -- PVR3 Debug and FSL
    C_DEBUG_ENABLED           : integer;
    C_NUMBER_OF_PC_BRK        : integer;
    C_NUMBER_OF_RD_ADDR_BRK   : integer;
    C_NUMBER_OF_WR_ADDR_BRK   : integer;
    C_FSL_LINKS               : integer;
    -- PVR4 Instruction Cache
    C_USE_ICACHE              : integer;
    C_ADDR_TAG_BITS           : integer;
    C_ICACHE_USE_FSL          : integer;
    C_ALLOW_ICACHE_WR         : integer;
    C_ICACHE_LINE_LEN         : integer;
    C_CACHE_BYTE_SIZE         : integer;
    C_ICACHE_ALWAYS_USED      : integer;
    -- PVR5 Data Cache 
    C_USE_DCACHE              : integer;
    C_DCACHE_ADDR_TAG         : integer;
    C_DCACHE_USE_FSL          : integer;
    C_ALLOW_DCACHE_WR         : integer;
    C_DCACHE_LINE_LEN         : integer;
    C_DCACHE_BYTE_SIZE        : integer;
    C_DCACHE_ALWAYS_USED      : integer;
    -- PVR6 Instruction Cache Base Address
    C_ICACHE_BASEADDR         : std_logic_vector(0 to 31);
    -- PVR7 Instruction Cache High Address
    C_ICACHE_HIGHADDR         : std_logic_vector(0 to 31);
    -- PVR8 Data Cache Base Address
    C_DCACHE_BASEADDR         : std_logic_vector(0 to 31);
    -- PVR9 Data Cache High Address
    C_DCACHE_HIGHADDR         : std_logic_vector(0 to 31);
    -- PVR10 Target
    C_TARGET                  : TARGET_FAMILY_TYPE;
    -- PVR11 MMU and reset value for MSR register
    C_USE_MMU                 : integer;
    C_MMU_DTLB_SIZE           : integer;
    C_MMU_ITLB_SIZE           : integer;
    C_MMU_TLB_ACCESS          : integer;
    C_MMU_ZONES               : integer;
    C_RESET_MSR               : std_logic_vector(MSR_REG_POS_TYPE)
    );
  port (
    -- Common signals.
    Clk             : in  std_logic;
    Reset           : in  std_logic;
    
    -- PVR read interface.
    MEM_PipeRun     : in  boolean;                   -- Move the memory stage
    MEM_PVR_Select  : in  std_logic_vector(0 to 3);  -- Select which PVR to read
    MEM_Sel_SPR_PVR : in  boolean;                   -- Select SPR processor version register
    WB_Sel_SPR_PVR  : in  boolean;                   -- Select SPR processor version register
    WB_PVR          : out PVR_TYPE                   -- PVR Read port 
    );
  end component PVR;

  -----------------------------------------------------------------------------
  -- Internal signal declarations
  -----------------------------------------------------------------------------

  -- outputs of "Register_File_I"
  signal gpr_op1 : DATA_TYPE;
  signal gpr_op2 : DATA_TYPE;
  signal gpr_op3 : DATA_TYPE;

  -- outputs of "Operand_Select_I"
  signal ex_op1_i : DATA_TYPE;
  signal ex_op2   : DATA_TYPE;
  signal ex_op3   : DATA_TYPE;

  -- prevent register duplication in XST, to avoid suboptimal packing in ISE
  attribute max_fanout : string;
  attribute max_fanout of ex_op1_i : signal is "1000000";
  attribute max_fanout of ex_op2   : signal is "1000000";
  attribute max_fanout of ex_op3   : signal is "1000000";

  signal ex_branch_cmp_op1     : DATA_TYPE;

  -- outputs of "ALU_I"
  signal ex_alu_result_i : DATA_TYPE;

  -- outputs of "Shift_Logic_Module_I"
  signal ex_shift_logic_result : DATA_TYPE;

  -- outputs of "MUL_Unit_I"
  signal wb_mul_result : DATA_TYPE;

  -- Barrel Shifter
  -- Number of bits to shift
  signal ex_bs_num_bits : BSNUM_TYPE;
  -- barrel shifter result
  signal mem_barrel_result : DATA_TYPE;
  
  -- outputs of "EX_MUX_I"
  signal ex_fwd : DATA_TYPE;

  -- outputs of "MEM_MUX_I"
  signal mem_fwd : DATA_TYPE;

  -- outputs of "WB_MUX_I"
  signal wb_fwd_i : DATA_TYPE;

  -- outputs of "Byte_Doublet_Handle_I"
  signal wb_steered_read_data : DATA_TYPE;
  signal ex_unalign_2lsb      : slv_0to1;

  -- outputs of "Data_Flow_Logic_I"
  signal ex_op1_2lsb       : slv_0to1;  -- 2 low bits of Op1
  signal ex_op2_2lsb       : slv_0to1;  -- 2 low bits of Op2
  signal mem_ex_result     : DATA_TYPE;
  signal wb_mem_result     : DATA_TYPE;
  signal wb_unalign_2lsb   : slv_0to1;
  signal mem_not_mul_op    : boolean;
  signal mem_not_fpu_instr : boolean;

  -- local MSR signals
  signal ex_alu_carry         : std_logic;
  signal ex_shift_carry       : std_logic;
  signal ex_carryin           : std_logic;

  signal ex_msr_i  : DATA_TYPE;
  signal mem_msr_i : DATA_TYPE;

  signal wb_ear : EAR_TYPE;
  signal wb_edr : EAR_TYPE;
  signal wb_esr : ESR_TYPE;
  signal wb_fsr : FSR_TYPE;
  signal wb_pvr : PVR_TYPE;

  signal WB_BTR : BTR_TYPE;

  signal wb_excep_return_addr : DATA_TYPE;
  
  -- local FSL signals
  signal ex_FSL_No: natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
  signal wb_FSL_No: natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on

  -- div result
  signal mem_div_result   : DATA_TYPE;
  signal ex_op1_zero_i    : boolean;
  signal mem_dividestall  : rboolean;
  signal mem_dividebyzero : rboolean;

  -- FPU Result
  signal wb_fpu_result    : DATA_TYPE;

  constant USE_D_OPB  : boolean := C_D_OPB = 1;  -- Not for C_D_PLB
  constant USE_ICACHE : boolean := C_USE_ICACHE = 1;
  constant USE_DCACHE : boolean := C_USE_DCACHE = 1;
  constant USE_FPU : boolean := (C_USE_FPU /= 0);

  signal enable_mem_barrel_result : DATA_TYPE;
  signal enable_mem_div_result    : DATA_TYPE;
  signal enable_mem_ex_result     : DATA_TYPE;

begin
  
  --------------------------------------------------------------------------
  -- Component Instantiations
  --------------------------------------------------------------------------

  ----------------------------------------
  -- Instance "Register_File_I"
  -- 32x32 bit register file
  -- Stages:
  -- OF  - reading of registers
  -- WB  - writing result
  ----------------------------------------
  Register_File_I : Register_File_gti
    generic map (
      C_TARGET => C_TARGET              -- [TARGET_FAMILY_TYPE]
      -- pragma xilinx_rtl_off
      ,
      C_U_SET  => C_U_SET               -- [string]
      -- pragma xilinx_rtl_on
    )
    port map (
      Clk      => Clk,                  -- [in  std_logic]

      OF_GPR_Op1_Rd_Addr => OF_GPR_Op1_Rd_Addr,  -- [in  GPR_ADDR_TYPE]
      GPR_Op1            => gpr_op1,             -- [out DATA_TYPE]

      OF_GPR_Op2_Rd_Addr => OF_GPR_Op2_Rd_Addr,  -- [in  GPR_ADDR_TYPE]
      GPR_Op2            => gpr_op2,             -- [out DATA_TYPE]

      OF_GPR_Op3_Rd_Addr => OF_GPR_Op3_Rd_Addr,  -- [in  GPR_ADDR_TYPE]
      GPR_Op3            => gpr_op3,             -- [out DATA_TYPE]

      WB_GPR_Wr_Addr => WB_GPR_Wr_Addr,              -- [in  GPR_ADDR_TYPE]
      WB_GPR_Wr      => WB_GPR_Wr,                   -- [in  boolean]
      WB_Fwd         => wb_fwd_i                       -- [in  DATA_TYPE]
      -- GPR_Read_For_Stores => gpr_read_for_stores  -- [out DATA_TYPE]
    );

  ----------------------------------------
  -- Instance "Operand_Select_I"
  -- Muxes to select operand 1 and operand 2
  -- Stages:
  -- OF  - inputs
  -- EX  - registered op1 and op2 outputs
  ----------------------------------------
  Operand_Select_I : Operand_Select_gti
    generic map (
      C_TARGET => C_TARGET              -- [TARGET_FAMILY_TYPE]
    )
    port map (
      Clk      => Clk,                  -- [in  std_logic]
      Reset    => Reset,                -- [in  std_logic]

      OF_PipeRun => OF_PipeRun,         -- [in  boolean]

      GPR_Op1 => gpr_op1,               -- [in  DATA_TYPE]
      GPR_Op2 => gpr_op2,               -- [in  DATA_TYPE]
      GPR_Op3 => gpr_op3,               -- [in  DATA_TYPE]

      OF_Imm_Data       => OF_Imm_Data,        -- [in  IMM16_TYPE]
      OF_Write_Imm_Reg  => OF_Write_Imm_Reg,   -- [in  boolean]
      OF_Read_Imm_Reg   => OF_Read_Imm_Reg,    -- [in  boolean]
      OF_Take_Interrupt => OF_Take_Interrupt,  -- [in  boolean]
      OF_Take_Ext_BRK   => OF_Take_Ext_BRK,    -- [in  boolean]
      OF_Take_Exception => OF_Take_Exception,  -- [in  boolean]

      OF_PC  => OF_PC,                  -- [in  DATA_TYPE]
      EX_MSR => ex_msr_i,               -- [in  DATA_TYPE]

      EX_Fwd  => ex_fwd,                -- [in  DATA_TYPE]
      MEM_Fwd => mem_fwd,               -- [in  DATA_TYPE]
      WB_Fwd  => wb_fwd_i,              -- [in  DATA_TYPE]

      OF_Op1_Sel_SPR_PC  => OF_Op1_Sel_SPR_PC,   -- [in  boolean]
      OF_Op1_Sel_SPR_MSR => OF_Op1_Sel_SPR_MSR,  -- [in  boolean]
      OF_Op1_Sel_SPR     => OF_Op1_Sel_SPR,      -- [in  boolean]

      OF_Op2_Sel_Imm => OF_Op2_Sel_Imm,
      OF_Op1_Sel => OF_Op1_Sel,         -- [in  std_logic_vector(0 to 1)]
      OF_Op2_Sel => OF_Op2_Sel,         -- [in  std_logic_vector(0 to 1)]
      OF_Op3_Sel => OF_Op3_Sel,         -- [in  std_logic_vector(0 to 1)]

      EX_Op1 => ex_op1_i,               -- [out DATA_TYPE]
      EX_Op2 => ex_op2,                 -- [out DATA_TYPE]
      EX_Op3 => ex_op3,                 -- [out DATA_TYPE]

      EX_Branch_CMP_Op1 => ex_branch_cmp_op1  -- [out DATA_TYPE]
      );

  EX_Op1 <= ex_op1_i;

  ----------------------------------------
  -- Instance "ALU_I"
  -- Arithmetic Logic Unit
  -- Stages:
  -- EX  - ALU and sign extension/mask
  ----------------------------------------
  ALU_I : ALU
    generic map (
      C_AREA_OPTIMIZED     => C_AREA_OPTIMIZED,
      C_TARGET => C_TARGET              -- [TARGET_FAMILY_TYPE]
    )
    port map (
      EX_ALU_Op      => EX_ALU_Op,       -- [in  slv_0to1]
      EX_CMP_Op      => EX_CMP_Op,       -- [in  boolean]
      EX_Unsigned_Op => EX_Unsigned_Op,  -- [in  boolean]
      EX_Use_Carry   => EX_Use_Carry,
      
      EX_CarryIn => ex_carryin,         -- [in  std_logic]
      EX_Op1     => ex_op1_i,           -- [in  DATA_TYPE]
      EX_Op2     => ex_op2,             -- [in  DATA_TYPE]

      EX_ALU_Result => ex_alu_result_i,  -- [out DATA_TYPE]
      EX_ALU_Carry  => ex_alu_carry      -- [out std_logic]
    );

--  EX_ALU_CarryOut <= ex_alu_carry;
  
  ----------------------------------------
  -- Instance "Shift_Logic_Module_I"
  -- Sign Extension, Shift logic, logic operations
  -- Stages: 
  -- EX - ex_shift_logic_result
  ----------------------------------------
  Shift_Logic_Module_I: Shift_Logic_Module_gti
    generic map (
      C_USE_PCMP_INSTR => C_USE_PCMP_INSTR,
      C_TARGET         => C_TARGET,
      C_U_SET          => C_U_SET
    )
    port map (
      EX_Op1                => ex_op1_i,
      EX_Op2                => ex_op2,
      EX_CarryIn            => ex_carryin,
      EX_Sext_Op            => EX_Sext_Op,
      EX_Shift_Op           => EX_Shift_Op,
      EX_Logic_Op           => EX_Logic_Op,
      EX_Sign_Extend_Sel    => EX_Sign_Extend_Sel,
      EX_Pattern_Cmp_Sel    => EX_Pattern_Cmp_Sel,
      EX_Logic_Sel          => EX_Logic_Sel,
      EX_Shift_Logic_Result => ex_shift_logic_result,
      EX_Shift_Carry        => ex_shift_carry
    );
  
  ----------------------------------------
  -- Instance "MUL_Unit_I"
  -- Hardware multiplier
  -- Stages: 
  -- EX  - 
  -- MEM -
  -- WB  -
  ----------------------------------------
  MUL_Unit_I : MUL_Unit
    generic map (
      C_TARGET     => C_TARGET,          -- [TARGET_FAMILY_TYPE]
      C_USE_HW_MUL => C_USE_HW_MUL,      -- [boolean]