data_flow_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      EX_PipeRun        : in  boolean;                   -- Move the execute stage
      MEM_Barrel_Result : out DATA_TYPE                  -- Barrel shifter result
    );
  end component Barrel_Shifter_gti;
  
  component WB_Mux is
    generic (
      C_TARGET         : TARGET_FAMILY_TYPE := VIRTEX4;
      C_FSL_EXCEPTION  : boolean := false;
      C_USE_EXCEPTIONS : boolean := false;
      C_USE_HW_MUL     : boolean := true;
      C_USE_FPU        : boolean := false;     -- Enable FPU?
      C_USE_MMU        : integer := 0;
      C_MMU_TLB_READ   : boolean := false;
      C_PVR            : integer := 0
      );  
    port (
      WB_Sel_DataBus_Read_Data : in boolean;
      WB_Steered_Read_Data     : in DATA_TYPE;

      WB_Sel_MEM_Res : in boolean;
      WB_MEM_Result  : in DATA_TYPE;

      WB_Sel_MUL_Res : in boolean;
      WB_Mul_Result  : in DATA_TYPE;

      WB_Sel_FPU_Res : in boolean;
      WB_FPU_Result  : in DATA_TYPE;

      WB_Sel_MMU_Res : in boolean;  -- WB mux select result from MMU
      WB_MMU_Result  : in DATA_TYPE;

      WB_Sel_SPR_ESR : in boolean;  -- Select SPR exception status register
      WB_ESR         : in ESR_TYPE;

      WB_Sel_SPR_EAR : in boolean;  -- Select SPR exception address register
      WB_EAR         : in EAR_TYPE;

      WB_Sel_SPR_EDR : in boolean;  -- Select SPR exception data register
      WB_EDR         : in EDR_TYPE;
  
      WB_Sel_SPR_FSR : in boolean;  -- Select SPR floating point status register
      WB_FSR         : in FSR_TYPE;

      WB_Sel_SPR_PVR : in boolean;  -- Select SPR processor version register
      WB_PVR         : in PVR_TYPE;

      WB_Sel_SPR_BTR : in boolean;  -- Select SPR Branch Target Register
      WB_BTR         : in BTR_TYPE;

      WB_Exception_Taken : in boolean;
      WB_PC              : in DATA_TYPE;

      WB_Fwd : out DATA_TYPE
    );
  end component WB_Mux;

  component Zero_Detect_gti is
    generic (
      C_TARGET          : TARGET_FAMILY_TYPE
    );
    port (
      EX_Op1_CMP_Equal   : in  boolean;
      EX_Op1_CMP_Equal_n : in  boolean;
      EX_Branch_CMP_Op1  : in  DATA_TYPE;
      EX_Op1_Zero        : out boolean
    );
  end component Zero_Detect_gti;

  component Byte_Doublet_Handle_gti
    generic (
      C_TARGET          :    TARGET_FAMILY_TYPE
      -- pragma xilinx_rtl_off
      ;
      C_U_SET           :    string
      -- pragma xilinx_rtl_on
    );
    port (
      Clk   : in std_logic;
      Reset : in std_logic;

      EX_PipeRun : in boolean;

      EX_Byte_Access    : in boolean;
      EX_Doublet_Access : in boolean;

      EX_Op1_2LSb : in slv_0to1;
      EX_Op2_2LSb : in slv_0to1;

      EX_Op3                       : in  DATA_TYPE;
      EX_DataBus_Write_Data        : out DATA_TYPE;
      EX_DataBus_Byte_Enable       : out DATA_BE_TYPE;
      MEM_DataBus_Write_Data       : out DATA_TYPE;
      MEM_DataBus_Byte_Enable      : out DATA_BE_TYPE;

      EX_Addr_Low_Bits : out slv_0to1;
      EX_UnAlign_2LSb  : out slv_0to1;
      WB_UnAlign_2LSb  : in  slv_0to1;

      WB_Byte_Access    : in boolean;
      WB_Doublet_Access : in boolean;

      WB_DataBus_Read_Data : in  DATA_TYPE;
      WB_Steered_Read_Data : out DATA_TYPE
      );
  end component Byte_Doublet_Handle_gti;

  component Data_Flow_Logic
    generic (
      C_MAX_FSL_LINKS  : natural
    );
    port (
      Clk   : in std_logic;
      Reset : in std_logic;

      OF_PipeRun  : in boolean;
      EX_PipeRun  : in boolean;
      MEM_PipeRun : in boolean;

      EX_Op1 : in DATA_TYPE;
      EX_Op2 : in DATA_TYPE;

      EX_Op1_2LSb : out slv_0to1;
      EX_Op2_2LSb : out slv_0to1;

      EX_Fwd  : in DATA_TYPE;
      MEM_Fwd : in DATA_TYPE;

      EX_FSL_No           : in  natural range 0 to C_MAX_FSL_LINKS-1;
      WB_FSL_No           : out natural range 0 to C_MAX_FSL_LINKS-1;
      
      EX_Is_BS_Instr     : in  boolean;
      EX_Is_Div_Instr    : in  boolean;
      MEM_EX_Result_Load : in  boolean;
      MEM_Sel_MEM_Res    : in  boolean;
      MEM_EX_Result      : out DATA_TYPE;
      WB_MEM_Result      : out DATA_TYPE;

      EX_Not_Mul_Op  : in  boolean;
      MEM_Not_Mul_Op : out boolean;

      EX_Not_FPU_Op   : in  boolean;
      MEM_Not_FPU_Op  : out boolean;

      EX_UnAlign_2LSb : in  slv_0to1;
      WB_UnAlign_2LSb : out slv_0to1;

      WB_Byte_Access    : in  boolean;
      WB_Quadlet_Access : in  boolean
    );
  end component Data_Flow_Logic;

  component msr_reg_gti
    generic (
      C_RESET_MSR      : MSR_TYPE;
      C_PVR            : integer;
      C_USE_MMU        : integer;
      C_USE_DIV        : boolean;
      C_USE_D_OPB      : boolean;
      C_FSL_LINKS      : integer;
      C_USE_ICACHE     : boolean;
      C_USE_DCACHE     : boolean;
      C_USE_EXCEPTIONS : boolean
    );
    port (
      Clk                  : in  std_logic;
      Rst                  : in  std_logic;
      EX_Op1               : in  DATA_TYPE;
      EX_Op2               : in  DATA_TYPE;
      EX_ALU_Carry         : in  std_logic;
      EX_Shift_Carry       : in  std_logic;
      EX_FSL_Carry         : in  std_logic;
      EX_FSL_Control_Error : in  std_logic;
      MEM_DivideByZero     : in  boolean;
      OF_PipeRun           : in  boolean;
      EX_PipeRun           : in  boolean;
      MEM_PipeRun          : in  boolean;
      WB_PipeRun           : in  boolean;
      EX_MSR_Load_ALU_C    : in  std_logic;
      EX_MSR_Load_Shift_C  : in  std_logic;
      EX_MSR_Load_FSL_C    : in  std_logic;
      EX_MSR_Set_IE        : in  std_logic;
      EX_MSR_Set_EE        : in  std_logic;
      EX_MSR_Set_SW_BIP    : in  std_logic;
      EX_MSR_Clear_EIP     : in  std_logic;
      EX_MSR_Clear_BIP     : in  std_logic;
      EX_MSR_Clear_VM_UM   : in  std_logic;
      EX_MTS_MSR           : in  std_logic;
      EX_MSRCLR            : in  std_logic;
      EX_MSRSET            : in  std_logic;
      EX_Restore_WB_MSR    : in  std_logic;
      MEM_MSR_Load_DZ      : in  std_logic;
      WB_MSR_Clear_IE      : in  std_logic;
      WB_MSR_Clear_EE      : in  std_logic;
      WB_MSR_Set_EIP       : in  std_logic;
      WB_MSR_Set_HW_BIP    : in  std_logic;
      OF_MSR               : out DATA_TYPE;
      EX_MSR               : out DATA_TYPE;
      MEM_MSR              : out DATA_TYPE;
      WB_MSR               : out DATA_TYPE
    );
  end component msr_reg_gti;

  component exception_registers_gti is
    generic (
      C_FSL_EXCEPTION  : boolean := false;
      C_MAX_FSL_LINKS  : natural;
      C_SAVE_PC_IN_EAR : boolean := false;
      C_USE_MMU        : integer
      );
    port (
      Clk                      : in  std_logic;
      Reset                    : in  std_logic;
      EX_PipeRun               : in  boolean;
      MEM_PipeRun              : in  boolean;
      EX_Instruction_Exception : in  boolean;
      EX_Data_Addr             : in  std_logic_vector(0 to 31);
      EX_PC                    : in  std_logic_vector(0 to 31);
      WB_PC                    : in  std_logic_vector(0 to 31);
      EX_Branch_Target         : in  std_logic_vector(0 to 31);
      EX_Load_BTR              : in  boolean;
      MEM_Sel_SPR_BTR          : in  boolean;  -- Select SPR Branch Target Register
      MEM_Sel_SPR_ESR          : in  boolean;  -- Select SPR exception status register
      MEM_Sel_SPR_EAR          : in  boolean;  -- Select SPR exception address register
      MEM_Sel_SPR_EDR          : in  boolean;  -- Select SPR exception data register
      WB_Clr_ESR               : in  boolean;
      WB_Load_EAR              : in  boolean;
      WB_Load_EDR              : in  boolean;
      WB_Load_ESR              : in  boolean;
      WB_Exception_Kind        : in  EXCEPTION_KIND_TYPE;
      WB_SW_Instr              : in  std_logic;
      WB_Word_Access           : in  std_logic;
      WB_Zone_Protect          : in  std_logic;
      WB_New_ESR_ESS_Rx        : in  GPR_ADDR_TYPE;
      WB_DelaySlot_Instr       : in  boolean;
      WB_Read_Imm_Reg          : in  boolean;
      WB_Read_Imm_Reg_1        : in  boolean;
      WB_FSL_No                : in  natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
      WB_MEM_Result            : in  DATA_TYPE;
      WB_BTR                   : out BTR_TYPE;
      WB_Excep_Return_Addr     : out std_logic_vector(0 to 31);
      WB_EAR                   : out EAR_TYPE;
      WB_EDR                   : out EDR_TYPE;
      WB_ESR                   : out ESR_TYPE
    );
  end component exception_registers_gti;

  component Div_unit_gti is
    generic (
      C_TARGET    : TARGET_FAMILY_TYPE;   -- Device family
      C_DATA_SIZE : natural range 8 to 64);
    port (
      Clk             : in  std_logic;
      Reset           : in  std_logic;
      OF_PipeRun      : in  boolean;
      EX_PipeRun      : in  boolean;
      EX_Start_Div    : in  boolean;
      EX_Op1_Zero     : in  boolean;
      EX_Div_Unsigned : in  boolean;
      EX_Op1          : in  std_logic_vector(0 to C_DATA_SIZE-1);
      EX_Op2          : in  std_logic_vector(0 to C_DATA_SIZE-1);
      MEM_Is_Div_Instr: in  boolean;
      MEM_Div_Result  : out std_logic_vector(0 to C_DATA_SIZE-1);
      MEM_Div_By_Zero : out boolean;
      MEM_Div_Stall   : out boolean);
  end component Div_unit_gti;

  component FPU is
    generic (
      C_TARGET        : TARGET_FAMILY_TYPE;
      C_USE_FPU       : integer;  -- Enable FPU?
      C_FPU_EXCEPTION : integer);
    port (
      Clk               : in  std_logic;      -- Clock
      Reset             : in  std_logic;      -- Reset
      OF_PipeRun        : in  boolean;  -- Move the operand fetch stage
      EX_PipeRun        : in  boolean;  -- Move the execute stage
      MEM_PipeRun       : in  boolean;  -- Move the memory stage
      EX_Op1            : in  DATA_TYPE;      -- First operand
      EX_Op2            : in  DATA_TYPE;      -- Second operand
      EX_FPU_Op         : in  FPU_OP_TYPE;    -- FPU operation
      EX_FPU_Cond       : in  FPU_COND_TYPE;  -- FPU comparison conditions
      EX_MTS_FSR        : in  std_logic;      -- MTS write to FSR
      EX_Start_FPU      : in  boolean;  -- Start the FPU
      EX_Not_FPU_Instr  : in  boolean;  -- Not an FPU instruction
      MEM_Not_FPU_Instr : in  boolean;  -- Not an FPU instruction
      MEM_Sel_SPR_FSR   : in  boolean;  -- Select SPR floating point status register
      MEM_FPU_Done      : out rboolean;  -- FPU is finished in the next cycle
      MEM_FPU_Stall     : out rboolean;  -- FPU is stalling Mem Stage
      MEM_FPU_Excep     : out rboolean;  -- FPU Exception
      WB_FPU_Excep      : out rboolean;  -- FPU Exception
      WB_FPU_Result     : out DATA_TYPE;      -- FPU Result
      WB_FSR            : out FSR_TYPE);      -- FPU Status Register
  end component FPU;
  
  component PVR is
  generic (
    -- PVR0 Basic
    C_PVR                     : integer;   -- Which PVR mode None=0, Basic=1, Full=2
    C_MB_VERSION              : std_logic_vector(0 to 7);
    C_PVR_USER1               : std_logic_vector(0 to 7);   -- User defined byte
    -- PVR1 User defined
    C_PVR_USER2               : std_logic_vector(0 to 31);   -- User defined word
    -- PVR2 Configuration
    C_D_OPB                   : integer;
    C_D_LMB                   : integer;
    C_I_OPB                   : integer;
    C_I_LMB                   : integer;
    C_INTERRUPT_IS_EDGE       : integer;
    C_EDGE_IS_POSITIVE        : integer;
    C_D_PLB                   : integer;
    C_I_PLB                   : integer;
    C_INTERCONNECT            : integer;
    C_USE_MSR_INSTR           : boolean;
    C_USE_PCMP_INSTR          : boolean;
    C_AREA_OPTIMIZED          : boolean;
    C_USE_BARREL              : boolean;
    C_USE_DIV                 : boolean;
    C_USE_HW_MUL              : boolean;
    C_USE_FPU                 : integer;
    C_USE_MUL64               : boolean;