data_flow_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    EX_Byte_Access               : in  boolean;   -- Data bus 8-bit write
    EX_Doublet_Access            : in  boolean;   -- Data bus 16-bit write
    EX_DataBus_Write_Data        : out DATA_TYPE;  -- Rd data from register file for writing to memory
    EX_DataBus_Byte_Enable       : out DATA_BE_TYPE;  -- Data bus byte enables
    MEM_DataBus_Write_Data       : out DATA_TYPE;  -- Rd data from register file for writing to memory
    MEM_DataBus_Byte_Enable      : out DATA_BE_TYPE;  -- Data bus byte enables
    EX_DataBus_Aligned_Addr_2LSb : out slv_0to1;  -- 2 LSb of data bus address aligned for current access

    ----------------------------------
    -- Ports to "Shift_Logic_Module_I"
    ----------------------------------
    EX_Sext_Op              : in  SEXT_OP_TYPE;       -- Sign extend operation: 8-bit, 16-bit, none
    EX_Shift_Op             : in  SHIFT_OP_TYPE;      -- Shift operation: sra, src, srl
    EX_Logic_Op             : in  LOGIC_OP_TYPE;      -- Logic operation: or, and, xor, andn
    EX_Sign_Extend_Sel      : in  boolean;            -- Shift logic mux, select sign extend
    EX_Pattern_Cmp_Sel      : in  boolean;            -- Shift logic mux, select PCMP
    EX_Logic_Sel            : in  boolean;            -- Shift logic mux, select logic

    ----------------------------------
    -- Ports to "Barrel_Shifter_I"
    ----------------------------------
    -- EX_Not_Barrel_Op  : in  boolean;                   -- Disable barrel shifter
    EX_Is_BS_Instr    : in  boolean;                   -- If this is an active BS instruction
    EX_Left_Shift     : in  boolean;                   -- Select left/right shift (side)
    EX_Arith_Shift    : in  boolean;                   -- Arithmetic/logical shift (type)

    ----------------------------------
    -- Ports to "Zero_Detect_I" for branches
    ----------------------------------
    EX_Op1_CMP_Equal        : in  boolean;            -- Test for equality
    EX_Op1_CMP_Equal_n      : in  boolean;            -- Test for inequality
    EX_Op1_Zero             : out boolean;            -- Is Ra zero?
    EX_Op1_Neg              : out boolean;            -- Is Ra negative?

    -------------------
    -- Div Unit signals
    -------------------
    EX_Is_Div_Instr : in  boolean;
    EX_Start_Div    : in  boolean;
    EX_Div_Unsigned : in  boolean;
    MEM_Is_Div_Instr: in  boolean;
    MEM_Div_By_Zero : out boolean;
    MEM_Div_Stall   : out boolean;

    --------------
    -- FPU signals
    --------------
    EX_FPU_Op         : in  FPU_OP_TYPE;     -- FPU operation
    EX_FPU_Cond       : in  FPU_COND_TYPE;   -- FPU comparison conditions
    EX_MTS_FSR        : in  std_logic;       -- MTS write to FSR
    EX_Start_FPU      : in  boolean;         -- Start the FPU
    EX_Not_FPU_Instr  : in  boolean;         -- Not an FPU instruction
    MEM_Sel_SPR_FSR   : in  boolean;         -- Select SPR floating point status register
    MEM_FPU_Stall     : out boolean;         -- FPU is stalling Mem Stage
    MEM_FPU_Excep     : out rboolean;        -- FPU Exception

    --------------------
    -- FSL Links signals
    --------------------
    FSL_Get_No            : out natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
    FSL_Get_Data          : in  std_logic_vector(0 to C_DATA_SIZE-1);  -- Data that is received
    EX_FSL_Control_Error  : in  std_logic;  -- A FSL Get control bit mismatch has occured
    FSL_Put_No            : out natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
    FSL_Put_Data          : out std_logic_vector(0 to C_DATA_SIZE-1);  -- Data that is received
    EX_FSL_Write_Carry    : in  std_logic;
    EX_FSL_Carry          : in  std_logic;
    MEM_EX_Result_Load    : in  boolean;

    -----------------------
    -- Ports to "MSR_Reg_I"
    -----------------------
    EX_MSR_Load_ALU_C     : in std_logic;             -- Load ALU carry bit
    EX_MSR_Load_Shift_C   : in std_logic;             -- Load shift logic carry bit
    EX_MSR_Load_FSL_C     : in std_logic;             -- Load FSL carry bit
    EX_MSR_Set_IE         : in std_logic;             -- IE bit when returning from interrupt
    EX_MSR_Set_EE         : in std_logic;             -- Set exceptions enabled bit
    EX_MSR_Clear_EIP      : in std_logic;             -- Clear exception in progress bit
    EX_MSR_Set_SW_BIP     : in std_logic;             -- Set BIP bit for BRK/BRKI
    EX_MSR_Clear_BIP      : in std_logic;             -- Clear break in progress bit
    EX_MSR_Clear_VM_UM    : in std_logic;             -- Clear VM and UM bits
    EX_MTS_MSR            : in std_logic;             -- MTS write to MSR
    EX_MSRCLR             : in std_logic;             -- MSRCLR
    EX_MSRSET             : in std_logic;             -- MSRSET
    EX_Restore_WB_MSR     : in std_logic;             -- Restore WB MSR to EX stage for exceptions

    MEM_MSR_Load_DZ : in std_logic;                   -- Load divide by zero bit
    WB_MSR_Clear_IE : in std_logic;                   -- Clear IE bit in MEM/WB stage
    WB_MSR_Clear_EE : in std_logic;                   -- Clear EE bit in MEM/WB stage
    WB_MSR_Set_EIP  : in std_logic;                   -- Set EIP bit in MEM/SB stage
    WB_MSR_Set_HW_BIP  : in std_logic;                -- Set BIP bit for ext_brk/ext_nm_brk

    OF_MSR  : out DATA_TYPE;                          -- OF stage MSR
    EX_MSR  : out DATA_TYPE;                          -- EX stage MSR
    MEM_MSR : out DATA_TYPE;                          -- MEM stage MSR
    WB_MSR  : out DATA_TYPE;                          -- WB stage MSR

    -----------------------------
    -- Exception register signals
    -----------------------------
    EX_Instruction_Exception : in  boolean;
    EX_PC                    : in  std_logic_vector(0 to 31);
    EX_Load_BTR              : in  boolean;
    WB_Clr_ESR               : in  boolean;
    WB_Load_EAR              : in  boolean;
    WB_Load_ESR              : in  boolean;
    WB_Load_EDR              : in  boolean;
    WB_Exception_Kind        : in  EXCEPTION_KIND_TYPE;
    WB_SW_Instr              : in  std_logic;
    WB_Word_Access           : in  std_logic;
    WB_Zone_Protect          : in  std_logic;
    WB_New_ESR_ESS_Rx        : in  GPR_ADDR_TYPE;
    WB_DelaySlot_Instr       : in  boolean;
    WB_Read_Imm_Reg          : in  boolean;
    WB_Read_Imm_Reg_1        : in  boolean;

    ----------------
    -- Cache signals
    ----------------

    ----------------
    -- PVR signals
    ----------------
    MEM_PVR_Select  : in std_logic_vector(0 to 3);  -- Select which PVR to read
    MEM_Sel_SPR_PVR : in boolean;                   -- Select SPR processor version register

    ----------------
    -- MMU signals
    ----------------
    EX_Op1                       : out DATA_TYPE;  -- EX operand

    ----------------
    -- Debug signals
    ----------------
    WB_Fwd                       : out DATA_TYPE;  -- WB stage result
    WB_DataBus_Steered_Read_Data : out DATA_TYPE  -- WB read from databus result

    ----------------
    -- Trace signals
    ----------------

    -- add these later

  );
end entity Data_Flow_gti;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of Data_Flow_gti is

  -----------------------------------------------------------------------------
  -- Constant declarations
  -----------------------------------------------------------------------------
  
  constant FSL_EXCEPTION_ON  : boolean := ( C_FSL_LINKS > 0 ) and (C_FSL_EXCEPTION /= 0) and (C_USE_EXTENDED_FSL_INSTR /= 0);
  
  
  -----------------------------------------------------------------------------
  -- Component declarations
  -----------------------------------------------------------------------------

  component Register_File_gti is
    generic (
      C_TARGET :    TARGET_FAMILY_TYPE
      -- pragma xilinx_rtl_off
      ;
      C_U_SET  :    string
      -- pragma xilinx_rtl_on
    );
    port (
      Clk        : in std_logic;

      OF_GPR_Op1_Rd_Addr : in  GPR_ADDR_TYPE;
      GPR_Op1            : out DATA_TYPE;

      OF_GPR_Op2_Rd_Addr : in  GPR_ADDR_TYPE;
      GPR_Op2            : out DATA_TYPE;

      OF_GPR_Op3_Rd_Addr : in  GPR_ADDR_TYPE;
      GPR_Op3            : out DATA_TYPE;

      WB_GPR_Wr_Addr : in GPR_ADDR_TYPE;
      WB_GPR_Wr      : in boolean;
      WB_Fwd         : in DATA_TYPE
      -- GPR_Read_For_Stores : out DATA_TYPE
    );
  end component Register_File_gti;

  component Operand_Select_gti is
    generic (
      C_TARGET :    TARGET_FAMILY_TYPE
    );
    port (
      Clk        : in std_logic;
      Reset      : in std_logic;

      OF_PipeRun : in boolean;

      GPR_Op1 : in DATA_TYPE;
      GPR_Op2 : in DATA_TYPE;
      GPR_Op3 : in DATA_TYPE;

      OF_Imm_Data       : in IMM16_TYPE;
      OF_Write_Imm_Reg  : in boolean;
      OF_Read_Imm_Reg   : in boolean;
      OF_Take_Interrupt : in boolean;
      OF_Take_Ext_BRK   : in boolean;
      OF_Take_Exception : in boolean;

      OF_PC            : in DATA_TYPE;
      EX_MSR           : in DATA_TYPE;

      EX_Fwd           : in DATA_TYPE;
      MEM_Fwd          : in DATA_TYPE;
      WB_Fwd           : in DATA_TYPE;

      OF_Op1_Sel_SPR_PC  : in boolean;
      OF_Op1_Sel_SPR_MSR : in boolean;
      OF_Op1_Sel_SPR     : in boolean;
      OF_Op2_Sel_Imm     : in boolean;

      OF_Op1_Sel         : in std_logic_vector(0 to 1); -- Op1 select 
      OF_Op2_Sel         : in std_logic_vector(0 to 1); -- Op2 select 
      OF_Op3_Sel         : in std_logic_vector(0 to 1); -- Op3 select 

      EX_Op1                  : out DATA_TYPE;
      EX_Op2                  : out DATA_TYPE;
      EX_Op3                  : out DATA_TYPE;

      EX_Branch_CMP_Op1       : out DATA_TYPE

      -- EX_OpSel_Op2_cpy        : out DATA_TYPE;

      -- Take_Interrupt          : in  boolean;
      -- Take_Ext_BRK            : in  boolean;
      -- Take_Exception          : in  boolean;

      -- word_r1_r2_unalignment  : out std_logic;
      -- word_r1_imm_unalignment : out std_logic;
      -- halfword_unalignment    : out std_logic
    );
  end component Operand_Select_gti;

  component ALU is
    generic (
      C_AREA_OPTIMIZED       : integer:= 0;
      C_TARGET :    TARGET_FAMILY_TYPE
    );
    port (
      EX_ALU_Op      : in slv_0to1;
      EX_CMP_Op : in boolean;
      EX_Unsigned_Op : in boolean;
      EX_Use_Carry   : in boolean;

      EX_CarryIn : in std_logic;
      EX_Op1     : in DATA_TYPE;
      EX_Op2     : in DATA_TYPE;

      EX_ALU_Result : out DATA_TYPE;
      EX_ALU_Carry  : out std_logic
    );
  end component ALU;

  component Shift_Logic_Module_gti
    generic (
      C_USE_PCMP_INSTR : boolean;
      C_TARGET         : TARGET_FAMILY_TYPE;
      C_U_SET          : string
    );
    port (
      EX_Op1                : in  DATA_TYPE;
      EX_Op2                : in  DATA_TYPE;
      EX_CarryIn            : in  std_logic;
      EX_Sext_Op            : in  SEXT_OP_TYPE;
      EX_Shift_Op           : in  SHIFT_OP_TYPE;
      EX_Logic_Op           : in  LOGIC_OP_TYPE;
      EX_Sign_Extend_Sel    : in  boolean;
      EX_Pattern_Cmp_Sel    : in  boolean;
      EX_Logic_Sel          : in  boolean;
      EX_Shift_Logic_Result : out DATA_TYPE;
      EX_Shift_Carry        : out std_logic
    );
  end component Shift_Logic_Module_gti;

  component MUL_Unit is
    generic (
      C_TARGET     : TARGET_FAMILY_TYPE;
      C_USE_HW_MUL : boolean := true;   -- Hardware multiplier
      C_USE_MUL64  : boolean := false   -- 64 bit result
    );
    port (
      Clk             : in  std_logic;  -- Clock
      Reset           : in  std_logic;  -- Reset
      EX_Not_Mul_Op   : in  boolean;    -- Disable multiplier
      MEM_Not_Mul_Op  : in  boolean;    -- Disable multiplier
      EX_Mulh_Instr   : in  boolean;    -- Multiply high
      EX_Mulhu_Instr  : in  boolean;    -- Unsigned multiply high
      EX_Mulhsu_Instr : in  boolean;    -- Signed*Unsigned multiply high instruction
      EX_Op1          : in  DATA_TYPE;  -- Execute stage operand 1
      EX_Op2          : in  DATA_TYPE;  -- Execute stage operand 2
      EX_PipeRun      : in  boolean;    -- Move the execute stage
      MEM_PipeRun     : in  boolean;    -- Move the memory stage
      WB_Mul_Result   : out DATA_TYPE   -- WB stage multiplier result
    );
  end component MUL_Unit;

  component Barrel_Shifter_gti is
    generic (
      C_TARGET     : TARGET_FAMILY_TYPE;
      C_USE_BARREL : boolean              := false       -- Hardware barrel shifter
    );
    port (
      Clk               : in  std_logic;                 -- Clock
      Reset             : in  std_logic;                 -- Reset
      EX_Op1            : in  DATA_TYPE;                 -- First operand (to be shifted)
      -- EX_Not_Barrel_Op  : in  boolean;                   -- Disable barrel shifter
      EX_Is_BS_Instr    : in  boolean;                   -- If this is an active BS instruction
      EX_Left_Shift     : in  boolean;                   -- Select left/right shift (side)
      EX_Arith_Shift    : in  boolean;                   -- Arithmetic/logical shift (type)
      EX_BS_Num_Bits    : in  BSNUM_TYPE;                -- Number of bits to shift