📄 data_flow_gti.vhd
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--SINGLE_FILE_TAG--------------------------------------------------------------------------------- $Id: data_flow_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $--------------------------------------------------------------------------------- data_flow.vhd - entity/architecture pair----------------------------------------------------------------------------------- ****************************************************************************-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.-- **-- ** This text contains proprietary, confidential information of-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,-- ** and may be used, copied and/or disclosed only pursuant to the-- ** terms of a valid license agreement with Xilinx, Inc. -- **-- ** Unmodified source code is guaranteed to place and route, -- ** function and run at speed according to the datasheet-- ** specification. Source code is provided "as-is", with no-- ** obligation on the part of Xilinx to provide support.-- **-- ** Xilinx Hotline support of source code IP shall only include-- ** standard level Xilinx Hotline support, and will only address-- ** issues and questions related to the standard released Netlist-- ** version of the core (and thus indirectly, the original core source-- **-- ** The Xilinx Support Hotline does not have access to source-- ** code and therefore cannot answer specific questions related-- ** to source HDL. The Xilinx Support Hotline will only be able-- ** to confirm the problem in the Netlist version of the core.-- **-- ** This copyright and support notice must be retained as part-- ** of this text at all times.-- ****************************************************************************----------------------------------------------------------------------------------- Filename: data_flow.vhd-- Version: v2.00a-- Description: Moves the data through the processor---- VHDL-Standard: VHDL'93--------------------------------------------------------------------------------- Structure: -- data_flow.vhd-- -- register file-- -- operand select-- -- ALU-- -- shift logic-- -- mul unit-- -- barrel shifter-- -- Write Back MUX-- -- zero detect-- -- Byte Doublet Handle-- -- Data flow logic-- -- MSR-- -- Exception Registers-- -- FSL-- -- Div unit-- -- FPU----------------------------------------------------------------------------------- Author: goran-- History:-- goran 2001-03-05 - First Version-- BLT 2001-04-12-- ^^^^^^-- Added U_SET for grouping RLOCs-- ~~~~~~-- goran 2001-06-13-- ^^^^^^-- New value to MSR is coming directly from shift_logic-- ~~~~~~-- BJS 2005-03-21-- ^^^^^^-- Updated for new pipeline-- ~~~~~~----------------------------------------------------------------------------------- Naming Conventions:-- active low signals: "*_n"-- clock signals: "clk", "*_clk"-- reset signals: "rst", "*_rst", "reset"-- generics: All uppercase, starting with: "C_"-- constants: All uppercase, not starting with: "C_"-- state machine next state: "*_next_state"-- state machine current state: "*_curr_state"-- pipelined signals: "*_d#"-- counter signals: "*_cnt_*" , "*_counter_*", "*_count_*"-- internal version of output port: "*_i"-- ports: Names begin with uppercase-- component instantiations: "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" ---- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that-- stage:---- IF -- instruction fetch-- OF -- operand fetch-- EX -- execute-- MEM -- memory-- WB -- write back-------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;use IEEE.numeric_std.all;---------------------------------------------------------------------------- Include MicroBlaze package for data types and ISA constants--------------------------------------------------------------------------library Microblaze_v7_10_a;use Microblaze_v7_10_a.MicroBlaze_ISA.all;use Microblaze_v7_10_a.MicroBlaze_Types.all;--------------------------------------------------------------------------------- Data_Flow-------------------------------------------------------------------------------entity Data_Flow_gti is generic ( C_DATA_SIZE : natural range 1 to 64 := 32; C_TARGET : TARGET_FAMILY_TYPE; -- Device family C_AREA_OPTIMIZED : integer := 0; -- pragma xilinx_rtl_off C_U_SET : string := "dataflow"; -- Name of unit -- pragma xilinx_rtl_on -- generics for "Operand_Select_I" C_USE_EXCEPTIONS : boolean := false; -- Enable exceptions? C_USE_BARREL : boolean := false; -- Use barrel shifter? C_USE_DIV : boolean := false; -- Enable divider? C_USE_HW_MUL : boolean := true; -- Use hardware multiplier? (Otherwise disable multiplier) C_USE_MUL64 : boolean := false; -- Use 64-bit multiplier result C_USE_FPU : integer := 0; -- Enable FPU? C_RESET_MSR : MSR_TYPE := (others => '0'); C_USE_PCMP_INSTR : boolean := false; -- Enable pattern compare instructions? C_USE_MSR_INSTR : boolean := false; -- Enable msrxxx instructions? C_FSL_DATA_SIZE : integer :=32; C_FSL_LINKS : integer := 0; -- Number of FSL links C_MAX_FSL_LINKS : natural; C_USE_EXTENDED_FSL_INSTR : integer := 0; C_USE_MMU : integer := 0; -- Which MMU mode C_MMU_TLB_READ : boolean := false; -- Generics used by PVR C_PVR : integer; -- Which PVR mode None=0, Basic=1, Full=2 C_MB_VERSION : std_logic_vector(0 to 7); C_PVR_USER1 : std_logic_vector(0 to 7); C_PVR_USER2 : std_logic_vector(0 to 31); C_INTERCONNECT : integer; C_D_OPB : integer; C_D_PLB : integer; C_D_LMB : integer; C_I_OPB : integer; C_I_PLB : integer; C_I_LMB : integer; C_INTERRUPT_IS_EDGE : integer; C_EDGE_IS_POSITIVE : integer; C_OPCODE_0x0_ILLEGAL : integer; C_UNALIGNED_EXCEPTIONS : integer; C_ILL_OPCODE_EXCEPTION : integer; C_IOPB_BUS_EXCEPTION : integer; C_DOPB_BUS_EXCEPTION : integer; C_IPLB_BUS_EXCEPTION : integer; C_DPLB_BUS_EXCEPTION : integer; C_DIV_ZERO_EXCEPTION : integer; C_FPU_EXCEPTION : integer; C_FSL_EXCEPTION : integer; C_DEBUG_ENABLED : integer; C_NUMBER_OF_PC_BRK : integer; C_NUMBER_OF_RD_ADDR_BRK : integer; C_NUMBER_OF_WR_ADDR_BRK : integer; C_USE_ICACHE : integer; C_ADDR_TAG_BITS : integer; C_ICACHE_USE_FSL : integer; C_ALLOW_ICACHE_WR : integer; C_ICACHE_LINE_LEN : integer; C_CACHE_BYTE_SIZE : integer; C_ICACHE_ALWAYS_USED : integer; C_USE_DCACHE : integer; C_DCACHE_ADDR_TAG : integer; C_DCACHE_USE_FSL : integer; C_ALLOW_DCACHE_WR : integer; C_DCACHE_LINE_LEN : integer; C_DCACHE_BYTE_SIZE : integer; C_DCACHE_ALWAYS_USED : integer; C_ICACHE_BASEADDR : std_logic_vector(0 to 31); C_ICACHE_HIGHADDR : std_logic_vector(0 to 31); C_DCACHE_BASEADDR : std_logic_vector(0 to 31); C_DCACHE_HIGHADDR : std_logic_vector(0 to 31); C_MMU_DTLB_SIZE : integer; C_MMU_ITLB_SIZE : integer; C_MMU_TLB_ACCESS : integer; C_MMU_ZONES : integer ); port ( Clk : in std_logic; -- Clock Reset : in std_logic; -- internal reset OF_PipeRun : in boolean; -- Move the operand fetch stage EX_PipeRun : in boolean; -- Move the execute stage MEM_PipeRun : in boolean; -- Move the memory stage WB_PipeRun : in boolean; -- Move the writeback stage ----------------------------- -- Ports to "Register_File_I" ----------------------------- WB_GPR_Wr_Addr : in GPR_ADDR_TYPE; -- General Purpose Register write address WB_GPR_Wr : in boolean; -- General Purpose Register write strobe OF_GPR_Op1_Rd_Addr : in GPR_ADDR_TYPE; -- General Purpose Register read address for Op1 OF_GPR_Op2_Rd_Addr : in GPR_ADDR_TYPE; -- General Purpose Register read address for Op2 OF_GPR_Op3_Rd_Addr : in GPR_ADDR_TYPE; -- General Purpose Register read address for Op3 ------------------------------ -- Ports to "Operand_Select_I" ------------------------------ OF_Imm_Data : in IMM16_TYPE; -- Opcode immediate data OF_Write_Imm_Reg : in boolean; -- Immediate register write strobe OF_Read_Imm_Reg : in boolean; -- Immediate register read strobe OF_PC : in DATA_TYPE; -- OF stage program counter OF_Take_Interrupt : in boolean; -- OF_Take_Ext_BRK : in boolean; OF_Take_Exception : in boolean; -- OF_Op1_Sel_SPR_PC : in boolean; -- Op1 select SPR program counter OF_Op1_Sel_SPR_MSR : in boolean; -- Op1 select SPR machine status register OF_Op1_Sel_SPR : in boolean; -- Op1 select special purpose register OF_Op2_Sel_Imm : in boolean; OF_Op1_Sel : in std_logic_vector(0 to 1); -- Op1 select OF_Op2_Sel : in std_logic_vector(0 to 1); -- Op2 select OF_Op3_Sel : in std_logic_vector(0 to 1); -- Op3 select -- Take_Interrupt : in boolean; -- Take_Extr_BRK : in boolean; -- Take_Exception : in boolean; -- MFS_Reg_Sel : in slv_0to1; -- EAR : in EAR_TYPE; -- ESR : in ESR_TYPE; -- word_r1_r2_unalignment : out std_logic; -- word_r1_imm_unalignment : out std_logic; -- halfword_unalignment : out std_logic; ------------------- -- Ports to "ALU_I" ------------------- EX_ALU_Op : in ALU_OP_TYPE; -- Which ALU operation to perform EX_CMP_Op : in boolean; -- Perform compare operation EX_Unsigned_Op : in boolean; -- Perform unsigned operation (rather than signed) EX_Use_Carry : in boolean; -- Use carry in-- EX_CarryIn : in std_logic; -- CarryIn bit (from MSR or forwarding logic)-- EX_ALU_CarryOut : out std_logic; -- CarryOut bit EX_ALU_Result : out DATA_TYPE; -- ALU result EX_Addr_Low_Bits : out std_logic_vector(0 to 1); -- ALU result ----------------------------------- -- Sign extension and byte handling ----------------------------------- -- Sign_ext8 : in boolean; -- Sign_ext16 : in boolean; WB_Byte_Access : in boolean; -- Read on data bus is 8-bits WB_Doublet_Access : in boolean; -- Read on data bus is 16-bits WB_Quadlet_Access : in boolean; -- Read on data bus is 32-bits -------------------------- -- MUL_Unit -------------------------- EX_Not_Mul_Op : in boolean; -- Disable multiplier EX_Mulh_Instr : in boolean; -- Multiply high EX_Mulhu_Instr : in boolean; -- Unsigned multiply high EX_Mulhsu_Instr : in boolean; -- Signed*Unsigned multiply high instruction -------------------------- -- Ports to "EX_MUX_I" -------------------------- EX_Sel_ALU : in boolean; -- EX mux select ALU EX_Sel_Shift : in boolean; -- EX mux select shift logic EX_Sel_FSL : in boolean; -- EX mux select fsl input -------------------------- -- Ports to "MEM_MUX_I" -------------------------- MEM_Sel_Barrel : in boolean; -- MEM mux select barrel shifter MEM_Sel_Div : in boolean; -- MEM mux select div unit MEM_Sel_MSR : in boolean; -- MEM mux select EX MSR MEM_Sel_EX_Res : in boolean; -- MEM mux select EX result MEM_Sel_MEM_Res: in boolean; -- MEM mux select result from MEM stage -------------------------- -- Ports to "WB_MUX_I" -------------------------- MEM_Sel_SPR_BTR : in boolean; -- Select SPR Branch Target Register MEM_Sel_SPR_ESR : in boolean; -- Select SPR exception status register MEM_Sel_SPR_EAR : in boolean; -- Select SPR exception address register MEM_Sel_SPR_EDR : in boolean; -- Select SPR exception data register WB_Sel_SPR_ESR : in boolean; -- Select SPR exception status register WB_Sel_SPR_EAR : in boolean; -- Select SPR exception address register WB_Sel_SPR_EDR : in boolean; -- Select SPR exception data register WB_Sel_SPR_FSR : in boolean; -- Select SPR floating point status register WB_Sel_SPR_PVR : in boolean; -- Select SPR processor version register WB_Sel_SPR_BTR : in boolean; -- WB mux select SPR Branch Target register WB_Sel_DataBus_Read_Data : in boolean; -- WB mux select DataBus_Read_Data WB_Sel_MEM_Res : in boolean; -- WB mux select result from MEM stage WB_Sel_MUL_Res : in boolean; -- WB mux select multiplier WB_Sel_FPU_Res : in boolean; -- WB mux select FPU WB_Sel_MMU_Res : in boolean; -- WB mux select MMU WB_MMU_Result : in DATA_TYPE; -- WB MMU result from MMU register read WB_PC : in DATA_TYPE; -- WB mux PC WB_Exception_Taken : in boolean; -- WB mux select exception PC WB_DataBus_Read_Data : in DATA_TYPE; -- Data read from data bus ----------------------------------- -- Ports to "Byte_Doublet_Handle_I" -----------------------------------⌨️ 快捷键说明
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