add_sub_with_const.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: add_sub_with_const.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- add_sub_with_const.vhd - Entity and architecture
--
--  ***************************************************************************
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--
-------------------------------------------------------------------------------
-- Filename:        add_sub_with_const.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              add_sub_with_const.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2004-09-30    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity add_sub_with_const is
  
  generic (
    Size   : natural := 10;
    Const0 : natural := 0;
    Const1 : natural := 127
    );
  port (
    Value : in  std_logic_vector(0 to Size-1);
    Sub   : in  std_logic;
    Sel   : in  std_logic;
    Res   : out std_logic_vector(0 to Size-1));

end entity add_sub_with_const;

library unisim;
use unisim.vcomponents.all;

architecture IMP of add_sub_with_const is

  constant const0_s : std_logic_vector(0 to Size-1) := std_logic_vector(to_unsigned(Const0, size));
  constant const1_s : std_logic_vector(0 to Size-1) := std_logic_vector(to_unsigned(Const1, size));

  signal addsub : std_logic_vector(0 to Size-1);
  signal carry  : std_logic_vector(0 to Size);
  
begin  -- architecture IMP

  carry(Size) <= Sub;

  AddSub_Block : for I in Size-1 downto 0 generate

    addsub(I) <= Sub xor (Value(I) xor ((Sel and Const1_s(I)) or ((not Sel) and Const0_s(I))));

    MUXCY_L_I1 : MUXCY_L
      port map (
        DI => Value(I),                 -- [in  std_logic S = 0]
        CI => Carry(I+1),               -- [in  std_logic S = 1]
        S  => addsub(I),                -- [in  std_logic (Select)]
        LO => Carry(I));                -- [out std_logic]        

    XOR_I : XORCY
      port map (
        LI => addsub(I),
        CI => Carry(I+1),
        O  => res(I));

  end generate AddSub_Block;
  

end architecture IMP;