shift_logic_bit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: shift_logic_bit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Shift_Logic_Bit - entity/architecture 
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        shift_logic_bit.vhd
-- Version:         v1.00a
-- Description:     Implements one bit of the shift logic     
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              shift_logic_bit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;


-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Shift_Logic_Bit is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE);
  port (
    Op1             : in  std_logic;
    Op2             : in  std_logic;
    Shifted         : in  std_logic;
    Sext            : in  std_logic;
    Logic_Oper      : in  std_logic_vector(0 to 1);
    Shift_Oper      : in  std_logic;
    Select_Logic    : in  boolean;
    -- Logic_Res       : out std_logic;
    Shift_Logic_Res : out std_logic
    );

end entity Shift_Logic_Bit;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

library Unisim;
use Unisim.vcomponents.all;

architecture IMP of Shift_Logic_Bit is
  signal logic_Res_i    : std_logic;
  signal shift_Res      : std_logic;
  signal select_Logic_I : std_logic;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
  
begin  -- architecture IMP

  -----------------------------------------------------------------------------
  -- Logic
  -- Logic_Oper  Logic_Res
  --   00        Op1 or Op2
  --   01        Op1 and Op2
  --   10        Op1 xor Op2
  --   11        Op1 and not Op2
  --
  --  Logic_Oper    Op1/Op2
  --                00  01  11  10
  --     00          0   1   1   1    1110
  --     01          0   0   1   0    1000
  --     11          0   0   0   1    0100
  --     10          0   1   0   1    0110
  -- Init String 0100 0110 1000 1110 (468E)
  -----------------------------------------------------------------------------
  Logic_LUT : LUT4
    generic map(
      INIT => X"468E"
      )
    port map (
      O  => logic_Res_i,                      -- [out]
      I0 => Op2,                            -- [in]
      I1 => Op1,                            -- [in]
      I2 => Logic_Oper(Logic_Oper'right),   -- [in]
      I3 => Logic_Oper(Logic_Oper'left) );  -- [in]

  -----------------------------------------------------------------------------
  -- Shift
  -- Shift_Oper  Shift_Res
  --   0        Shifted
  --   1        Op1 or Sext
  --
  --  Shift_Oper,Sext    Op1/Shifted
  --                   00  01  11  10
  --     00             0   1   1   0    1010
  --     01             0   1   1   0    1010
  --     11             1   1   1   1    1111
  --     10             0   0   1   1    1100
  -- Init String 1111 1100 1010 1010 (FCAA)
  -----------------------------------------------------------------------------
  Shift_LUT : LUT4
    generic map(
      INIT => X"FCAA"
      )
    port map (
      O  => shift_Res,                  -- [out]
      I0 => Shifted,                    -- [in]
      I1 => Op1,                        -- [in]
      I2 => Sext,                       -- [in]
      I3 => Shift_Oper);                -- [in]


  -----------------------------------------------------------------------------
  -- The Mux between Logic results and Shift results
  -----------------------------------------------------------------------------

  select_Logic_I <= '1' when Select_Logic else '0';

  Shift_Logic_Mux : MUXF5
    port map (
      I0 => shift_Res,                  -- [in]
      I1 => logic_Res_i,                  -- [in]
      S  => select_Logic_I,             -- [in]
      O  => Shift_Logic_Res);           -- [out]

  -- Logic_Res <= logic_Res_i;
  
end architecture IMP;