address_data_hit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: address_data_hit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- address_data_hit.vhd
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        address_data_hit.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              address_data_hit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2001-10-30    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;

entity address_data_hit is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE;
    No_Bits  : natural            := 32);
  port (
    Address  : in  std_logic_vector(0 to No_Bits-1);
    Data     : in  std_logic_vector(0 to No_Bits-1);
    Armed    : in  std_logic;
    TClk     : in  std_logic;
    TDI      : in  std_logic;
    SRL16_En : in  std_logic;
    Hit      : out std_logic
    );
end entity address_data_hit;

library unisim;
use unisim.vcomponents.all;

architecture IMP of address_data_hit is

  signal addr_carry      : std_logic_vector(0 to 8);
  signal addr_SRL16_MC15 : std_logic_vector(0 to 8);
  signal addr_SRL16_Sel  : std_logic_vector(0 to 7);

  signal data_carry      : std_logic_vector(0 to 8);
  signal data_SRL16_MC15 : std_logic_vector(0 to 8);
  signal data_SRL16_Sel  : std_logic_vector(0 to 7);

begin  -- architecture IMP

  Using_FPGA : if (C_TARGET /= RTL) generate
  begin
    
    MUXCY_Pre : MUXCY
      port map (
        DI => '0',                      -- [in  std_logic]
        CI => '1',                      -- [in  std_logic]
        S  => armed,                    -- [in  std_logic]
        O  => addr_carry(8));           -- [out std_logic]

    addr_SRL16_MC15(8) <= TDI;

    Addr_Compare : for I in 7 downto 0 generate
     Addr_SRLC16E_I : SRLC16E
        port map (
          CE  => SRL16_En,            -- [in  std_logic]
          D   => Addr_SRL16_MC15(I+1),       -- [in  std_logic]
          Clk => TClk,                -- [in  std_logic]
          A0  => Address(31-I*4),     -- [in  std_logic]
          A1  => Address(30-I*4),     -- [in  std_logic]
          A2  => Address(29-I*4),     -- [in  std_logic]
          A3  => Address(28-I*4),     -- [in  std_logic]
          Q   => Addr_SRL16_Sel(I),        -- [out std_logic]
          Q15 => Addr_SRL16_MC15(I));    -- [out std_logic]

      MUXCY_1 : MUXCY
        port map (
          DI => '0',                  -- [in  std_logic]
          CI => Addr_carry(I+1),             -- [in  std_logic]
          S  => Addr_SRL16_Sel(I),         -- [in  std_logic]
          O  => Addr_carry(I));          -- [out std_logic]
    end generate Addr_Compare;

    data_carry(8)      <= Addr_carry(0);
    data_SRL16_MC15(8) <= Addr_SRL16_MC15(0);
    
    Data_Compare : for I in 7 downto 0 generate
     Data_SRLC16E_I : SRLC16E
        port map (
          CE  => SRL16_En,            -- [in  std_logic]
          D   => Data_SRL16_MC15(I+1),       -- [in  std_logic]
          Clk => TClk,                -- [in  std_logic]
          A0  => Data(31-I*4),     -- [in  std_logic]
          A1  => Data(30-I*4),     -- [in  std_logic]
          A2  => Data(29-I*4),     -- [in  std_logic]
          A3  => Data(28-I*4),     -- [in  std_logic]
          Q   => Data_SRL16_Sel(I),        -- [out std_logic]
          Q15 => Data_SRL16_MC15(I));    -- [out std_logic]

      MUXCY_1 : MUXCY
        port map (
          DI => '0',                  -- [in  std_logic]
          CI => Data_carry(I+1),             -- [in  std_logic]
          S  => Data_SRL16_Sel(I),         -- [in  std_logic]
          O  => Data_carry(I));          -- [out std_logic]
    end generate Data_Compare;
    
    hit <= data_carry(data_carry'left);
    
  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate
    subtype SRL16_TYPE is std_logic_vector(0 to 15);
    type    SRL16_ARRAY_TYPE is array (0 to 15) of SRL16_TYPE;

    signal srl16_Array : SRL16_ARRAY_TYPE;
  begin

    Load_SRL16s : process (TClk) is
    begin  -- process Load_SRL16s
      if TClk'event and TClk = '1' then  -- rising clock edge
        if (SRL16_En = '1') then
          for I in 15 downto 0 loop
            if (I /= 15) then
              srl16_Array(I) <= srl16_Array(I+1)(15) & srl16_Array(I)(0 to 14);
            else
              srl16_Array(I) <= TDI & srl16_Array(I)(0 to 14);
            end if;
          end loop;  -- I
        end if; 
      end if;
    end process Load_SRL16s;

    Hit_Detect : process (srl16_Array, Armed, Address, Data) is
      variable local_hit  : std_logic;
      variable temp_srl16 : SRL16_TYPE;
    begin  -- process Hit_Detect
      if (Armed = '1') then
        local_hit := '1';
        for I in 0 to 7 loop
          temp_srl16 := srl16_Array(I+8);
          if temp_srl16(to_integer(unsigned(Address(I*4 to I*4+3)))) = '0' then
            local_hit := '0';
          end if;
        end loop;  -- I
        for I in 0 to 7 loop
          temp_srl16 := srl16_Array(I);
          if temp_srl16(to_integer(unsigned(Data(I*4 to I*4+3)))) = '0' then
            local_hit := '0';
          end if;
        end loop;  -- I
        hit <= local_hit;
      else
        hit <= '0';
      end if;
    end process Hit_Detect;

  end generate Using_RTL;
end architecture IMP;