dcache_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

          generic map (C_TARGET => C_TARGET)              -- [TARGET_FAMILY_TYPE]
          port map (Carry_IN  => valid_check_carry(I+1),  -- [in  std_logic]
                    A         => valid_check_sel(I),      -- [in  std_logic]
                    Carry_OUT => valid_check_carry(I));   -- [out std_logic]

      end generate valid_check_cacheline;

      mem_cache_hit <= valid_check_carry(0);
    end generate Using_8Line_6LUT;
    
    mem_cache_hit_pending <= mem_tag_hit and not mem_tag_bits(to_integer(unsigned(temp_Data_Addr)));

  end generate Valid_check_with_8word_cacheline;

  -- When cacheline size is 4 we do the valid check as part of the carry chain
  Valid_Check_With_4word_Cacheline : if (C_CACHELINE_SIZE = 4) generate
    signal temp_Data_Addr    : std_logic_vector(0 to CACHELINE_BITS-1);
  begin
    temp_Data_Addr     <= mem_mch_addr(30-CACHELINE_BITS to 29);
                
    Using_4Line_4LUT : if ( not C_LUT6_OPTIMIZED ) generate
      signal valid_check_sel   : std_logic_vector(0 to 1);
      signal valid_check_carry : std_logic;
    begin
      --check mem_tag_bits(2 to 3)
      valid_check_sel(0) <= '1' when (temp_Data_Addr(0) = '0') or
                            ((temp_Data_Addr(1) = '1' and mem_tag_bits(3) = '1') or
                             (temp_Data_Addr(1) = '0' and mem_tag_bits(2) = '1'))
                            else '0';
      valid_check_carry_and_I : carry_and
        generic map (C_TARGET => C_TARGET)          -- [TARGET_FAMILY_TYPE]
        port map (Carry_IN  => mem_tag_hit,         -- [in  std_logic]
                  A         => valid_check_sel(0),  -- [in  std_logic]
                  Carry_OUT => valid_check_carry);  -- [out std_logic]
  
      --check mem_tag_bits(0 to 1)
      valid_check_sel(1) <= '1' when (temp_Data_Addr(0) = '1') or
                            ((temp_Data_Addr(1) = '1' and mem_tag_bits(1) = '1') or
                             (temp_Data_Addr(1) = '0' and mem_tag_bits(0) = '1'))
                            else '0';
      valid_check_carry_and_2 : carry_and
        generic map (C_TARGET => C_TARGET)          -- [TARGET_FAMILY_TYPE]
        port map (Carry_IN  => valid_check_carry,   -- [in  std_logic]
                  A         => valid_check_sel(1),  -- [in  std_logic]
                  Carry_OUT => mem_cache_hit);      -- [out std_logic]

    end generate Using_4Line_4LUT;
    
    Using_4Line_6LUT : if ( C_LUT6_OPTIMIZED ) generate
      signal valid_check_sel   : std_logic;
    begin
      -- temp_Data_Addr(0 to 1) = "11" <=> tag_bits(3)
      -- temp_Data_Addr(0 to 1) = "10" <=> tag_bits(2)
      -- temp_Data_Addr(0 to 1) = "01" <=> tag_bits(1)
      -- temp_Data_Addr(0 to 1) = "00" <=> tag_bits(0)
      valid_check_sel  <= mem_tag_bits(3) when (temp_Data_Addr(0 to 1) = "11") else 
                          mem_tag_bits(2) when (temp_Data_Addr(0 to 1) = "10") else 
                          mem_tag_bits(1) when (temp_Data_Addr(0 to 1) = "01") else 
                          mem_tag_bits(0) when (temp_Data_Addr(0 to 1) = "00") else 
                          '0';
      
      lut6_valid_check_carry_and : carry_and
        generic map (C_TARGET => C_TARGET)        -- [TARGET_FAMILY_TYPE]
        port map (Carry_IN  => mem_tag_hit,       -- [in  std_logic]
                  A         => valid_check_sel,   -- [in  std_logic]
                  Carry_OUT => mem_cache_hit);    -- [out std_logic]

    end generate Using_4Line_6LUT;

    mem_cache_hit_pending <= mem_tag_hit and not mem_tag_bits(to_integer(unsigned(temp_Data_Addr)));
  end generate Valid_Check_With_4word_Cacheline;

  -- read cache hit can either be a direct read hit from the cache or a read
  -- into a cacheline that is currently being written into cache
  mem_read_cache_hit_direct_sel <= not mem_write_req;
  mem_read_cache_hit_direct_carry_and : carry_and
    generic map (C_TARGET => C_TARGET)  -- [TARGET_FAMILY_TYPE]
    port map (Carry_IN  => mem_cache_hit,                  -- [in  std_logic]
              A         => mem_read_cache_hit_direct_sel,  -- [in  std_logic]
              Carry_OUT => mem_read_cache_hit_direct);     -- [out std_logic]
  
  mem_read_cache_hit_posted <= (cacheline_copy_hit and not mem_write_req);

--    mem_read_cache_hit        <= mem_read_cache_hit_direct or mem_read_cache_hit_posted;
  mem_read_cache_hit_carry_or : carry_or
    generic map (C_TARGET => C_TARGET)                 -- [TARGET_FAMILY_TYPE]
    port map (Carry_IN  => mem_read_cache_hit_direct,  -- [in  std_logic]
              A         => mem_read_cache_hit_posted,  -- [in  std_logic]
              Carry_OUT => mem_read_cache_hit);        -- [out std_logic]

--    dcache_data_strobe_i <= mem_read_cache_hit or
--                            -- for write without a write update cache conflict
--                            (mem_Write_Allowed and (mem_data_write or mem_Data_Written) and (mem_data_updated or mem_write_cache_miss)) or
--                            -- for write where MCH writes is done before the
--                            -- write to cache has happened
--                            (update_cache_posted_write_done);

  dcache_data_strobe_sel <= (mem_Write_Allowed and (mem_data_write or mem_Data_Written) and (mem_data_updated or mem_write_cache_miss_delayed)) or
                            -- for write where MCH writes is done before the
                            -- write to cache has happened
                            (update_cache_posted_write_done);
  dcache_data_strobe_sel_carry_or : carry_or
    generic map (C_TARGET => C_TARGET)              -- [TARGET_FAMILY_TYPE]
    port map (Carry_IN  => mem_read_cache_hit,      -- [in  std_logic]
              A         => dcache_data_strobe_sel,  -- [in  std_logic]
              Carry_OUT => dcache_data_strobe_ii);   -- [out std_logic]

  Use_XX_Accesses_Hit : if (C_DCACHE_ALWAYS_USED /= 0) generate
    dcache_data_strobe_sel2_carry_or : carry_or
      generic map (C_TARGET => C_TARGET)             -- [TARGET_FAMILY_TYPE]
      port map (Carry_IN  => dcache_data_strobe_ii,  -- [in  std_logic]
                A         => xx_valid_data,          -- [in  std_logic]
                Carry_OUT => dcache_data_strobe_i);  -- [out std_logic]
  
  end generate Use_XX_Accesses_Hit;

  No_XX_Accesses2: if (C_DCACHE_ALWAYS_USED = 0) generate
    dcache_data_strobe_i <= dcache_data_strobe_ii;
  end generate No_XX_Accesses2;

--    mem_read_cache_miss <= mem_Valid_Req and mem_tag_miss and not mem_write_req;
  mem_read_cache_miss_sel <= mem_Valid_Req and not mem_write_req;
  mem_read_cache_miss_sel_carry_and : carry_and
    generic map (C_TARGET => C_TARGET)               -- [TARGET_FAMILY_TYPE]
    port map (Carry_IN  => mem_tag_miss,             -- [in  std_logic]
              A         => mem_read_cache_miss_sel,  -- [in  std_logic]
              Carry_OUT => mem_read_cache_miss_i);   -- [out std_logic]

  Use_XX_Accesses3 : if (C_DCACHE_ALWAYS_USED /= 0) generate
    xx_access_read_miss : carry_or
      generic map (
        C_TARGET => C_TARGET)                -- [TARGET_FAMILY_TYPE]
      port map (
        Carry_IN  => mem_read_cache_miss_i,  -- [in  std_logic]
        A         => xx_access,              -- [in  std_logic]
        Carry_OUT => mem_read_cache_miss);   -- [out std_logic]
  end generate Use_XX_Accesses3;

  No_XX_Accesses3: if (C_DCACHE_ALWAYS_USED = 0) generate
    mem_read_cache_miss <= mem_read_cache_miss_i;
  end generate No_XX_Accesses3;
  
  -----------------------------------------------------------------------------
  -- Write to MCH for
  -- 1. Read cache misses 
  -- 2. Valid write accesses always writes to MCH (write-through)
  -----------------------------------------------------------------------------
--    dcache_fsl_request <= ( (mem_read_cache_miss and mem_first_cycle)
--                            or
--                            (mem_write_req and mem_Valid_Req and not mem_Data_Written));

--    dcache_FSL_OUT_Write_i <= not DCACHE_FSL_OUT_Full and (dcache_fsl_request or dcache_fsl_request_hold);
  dcache_fsl_request_carry_and : carry_and
    generic map (C_TARGET => C_TARGET)                 -- [TARGET_FAMILY_TYPE]
    port map (Carry_IN  => mem_read_cache_miss,        -- [in  std_logic]
              A         => mem_first_cycle,            -- [in  std_logic]
              Carry_OUT => dcache_fsl_request_part1);  -- [out std_logic]

  dcache_fsl_request_sel <= mem_write_req and mem_valid_req_XX and not mem_Data_Written;
  dcache_fsl_request_carry_or : carry_or
    generic map (C_TARGET => C_TARGET)  -- [TARGET_FAMILY_TYPE]
    port map (Carry_IN  => dcache_fsl_request_part1,     -- [in  std_logic]
              A         => dcache_fsl_request_sel,       -- [in  std_logic]
              Carry_OUT => dcache_fsl_request);          -- [out std_logic]

--    dcache_FSL_OUT_Write_i <= not DCACHE_FSL_OUT_Full and (dcache_fsl_request or dcache_fsl_request_hold);
  dcache_fsl_out_write_carry_or : carry_or
    generic map (C_TARGET => C_TARGET)  -- [TARGET_FAMILY_TYPE]
    port map (Carry_IN  => dcache_fsl_request,           -- [in  std_logic]
              A         => dcache_fsl_request_hold,      -- [in  std_logic]
              Carry_OUT => dcache_fsl_out_write_part1);  -- [out std_logic]

  dcache_fsl_out_write_sel1 <= not DCACHE_FSL_OUT_Full;
  dcache_fsl_out_write_carry_and : carry_and
    generic map (C_TARGET => C_TARGET)  -- [TARGET_FAMILY_TYPE]
    port map (Carry_IN  => dcache_fsl_out_write_part1,     -- [in  std_logic]
              A         => dcache_fsl_out_write_sel1,      -- [in  std_logic]
              Carry_OUT => dcache_FSL_OUT_Write_i);        -- [out std_logic]
  
  -----------------------------------------------------------------------------
  -- Generating signals if we got a hit or a miss
  -----------------------------------------------------------------------------

  -- Read miss when addr part of the tags doesn't match

--  -- read cache hit can either be a direct read hit from the cache or a read
--  -- into a cacheline that is currently being written into cache
--  mem_read_cache_hit_direct <= mem_cache_hit and not mem_write_req;
--  mem_read_cache_hit_posted <= (cacheline_copy_hit and not mem_write_req);
--  mem_read_cache_hit        <= mem_read_cache_hit_direct or mem_read_cache_hit_posted;

  -- write cache hit can either a direct write hit or a pending write hit where
  -- we have to wait for the data in the cacheline to be written first to the
  -- memory and that we are allowed to write to the cache (MCH not currently writing).
  mem_write_cache_hit_direct <= mem_write_req and mem_cache_hit and ((not DCACHE_FSL_IN_Exists) or mem_data_updated);
  mem_write_cache_hit_posted <= mem_write_req and mem_cache_hit_pending_delayed and (cacheline_copy_hit or cacheline_copy_hit_hold) and
                                ((not DCACHE_FSL_IN_Exists) or mem_data_updated);
  mem_write_cache_hit        <= mem_write_cache_hit_direct or mem_write_cache_hit_posted;

  -- write cache miss when the addr part of the tags doesn't match
  mem_write_cache_miss <= mem_Valid_Req_XX and mem_write_req and mem_tag_miss;

  Delay_Write_Signales : process (Clk) is
  begin  -- process Delay_Write_Signales
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active high)
        mem_write_cache_miss_delayed  <= '0';
        mem_write_cache_hit_delayed   <= '0';
        mem_cache_hit_pending_delayed <= '0';
      else
        mem_write_cache_miss_delayed  <= mem_write_cache_miss;
        mem_write_cache_hit_delayed   <= mem_write_cache_hit;
        mem_cache_hit_pending_delayed <= mem_cache_hit_pending;
      end if;
    end if;

  end process Delay_Write_Signales;

  MEM_DCache_Data_strobe <= dcache_data_strobe_i;

  -- Need to delay data one clock cycle into the WB stage
  Read_data_DFF : process (Clk) is
  begin  -- process Read_data_DFF
    if Clk'event and Clk = '1' then       -- rising clock edge
      if dcache_data_strobe_i = '0' then  -- synchronous reset (active high)
        WB_DCache_Valid_Read_data <= (others => '0');
      else
        if (xx_valid_data = '1') or (use_cacheline_copy = '1') then
          WB_DCache_Valid_Read_data <= cacheline_copy_data;
        else
          WB_DCache_Valid_Read_data <= mem_cachehit_data;
        end if;
      end if;
    end if;
  end process Read_data_DFF;

  -----------------------------------------------------------------------------
  -- Setting up the signals for the tag memory
  -----------------------------------------------------------------------------

  ex_tag_addr <= EX_DataBus_Addr(30 - CACHELINE_BITS - Tag_Addr_Size to 29-CACHELINE_BITS);

  -- Handling the write signal to the tag memory
  cacheline_update_write <= (others => DCACHE_FSL_IN_Exists);
  -- Only write to tag on Cacheline updates or with the WDC instruction
  mem_new_tag_write_i    <= cacheline_update_write when (DCACHE_FSL_IN_Exists = '1') and (cache_updated_allowed = '1') else "0000";
  mem_new_tag_write      <= (others => '1')        when WB_Write_DCache            else mem_new_tag_write_i;

  ---------------------------------------------------------------------------
  -- The tag memory
  ---------------------------------------------------------------------------
  TAG_RAM_Module : RAM_Module
    generic map (
      C_TARGET     => C_TARGET,
      C_DATA_WIDTH => Tag_Word_Size,    -- [natural range 1 to 32]
      C_ADDR_WIDTH => Tag_Addr_Size,    -- [natural range 1 to 14]
      C_FORCE_BRAM => Tag_Force_BRAM)   -- [boolean]
    port map (
      -- PORT A is for the EX stage for checking for cache hit
      CLKA      => CLK,                 -- [in  std_logic]
      WEA       => null4 ,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
      ENA       => ram_enable,         -- [in  std_logic]
      ADDRA     => ex_tag_addr,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INA  => null_tag_data,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTA => mem_tag_bits,  -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]
      -- PORT B is for writing in a cacheline or for a write cachehit
      CLKB      => CLK,                 -- [in  std_logic]
      WEB       => mem_new_tag_write,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
      ENB       => '1',                 -- [in  std_logic]
      ADDRB     => mem_new_tag_addr,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INB  => mem_new_tag_bits,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTB => open);   -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]

  -----------------------------------------------------------------------------
  -- Handling when writes are allowed to happen to the cache
  -----------------------------------------------------------------------------

  -- Write misses are allowed to write when the write port is free (No MCH updates)
  mem_Write_Allowed_on_miss <= mem_write_cache_miss_delayed and not (DCACHE_FSL_IN_Exists);

  -- Keep the signal alive until we move the pipeline
  mem_Write_Allowed_on_miss_hold_DFF : process (Clk) is
  begin  -- process mem_Write_Allowed_on_miss_hold_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active high)
        mem_Write_Allowed_on_miss_hold <= '0';
      else
        if (Ex_piperun) then
          mem_Write_Allowed_on_miss_hold <= '0';
        elsif (mem_Write_Allowed_on_miss = '1') then
          mem_Write_Allowed_on_miss_hold <= '1';
        end if;
      end if;
    end if;
  end process mem_Write_Allowed_on_miss_hold_DFF;

  -- Write hits are allowed to write when the Write Port is free (No MCH updates)
  mem_Write_Allowed_on_hit <= (not(DCACHE_FSL_IN_Exists) and mem_write_cache_hit_delayed);
  mem_Write_Allowed        <= (mem_Write_Allowed_on_miss or mem_Write_Allowed_on_miss_hold) or mem_Write_Allowed_on_hit;


  --***************************************************************************
  --***************************************************************************
  --
  --  MCH interface
  --
  --***************************************************************************
  --***************************************************************************

  -- XCL Clocks
  DCACHE_FSL_IN_Clk  <= Clk;
  DCACHE_FSL_OUT_Clk <= Clk;

  -----------------------------------------------------------------------------
  -- Need to remember the FSL request if the FSL out fifo was full
  -----------------------------------------------------------------------------
  Remember_FSL_Write : process (Clk) is
  begin  -- process Remember_FSL_Write
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        dcache_fsl_request_hold <= '0';
      else
        if (dcache_fsl_request and DCACHE_FSL_OUT_Full) = '1' then
          dcache_fsl_request_hold <= '1';
        end if;
        if (dcache_fsl_request_hold and not DCACHE_FSL_OUT_Full) = '1' then
          dcache_fsl_request_hold <= '0';
        end if;
      end if;
    end if;
  end process Remember_FSL_Write;