dcache_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: dcache_gti.vhd,v 1.2 2007/12/13 13:56:42 stefana Exp $
-------------------------------------------------------------------------------
-- dcache_gti.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
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--  **  information of Xilinx, Inc. , is distributed by                      **
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--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
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--  **  to confirm the problem in the Netlist version of the core.           **
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--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        dcache_gti.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              dcache_gti.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/12/13 13:56:42 $
--
-- History:
--   goran  2005-09-16    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-- pragma xilinx_rtl_off
library unisim;
use unisim.vcomponents.all;
-- pragma xilinx_rtl_on

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity DCache_gti is
  generic (
    C_TARGET             : TARGET_FAMILY_TYPE;
    C_DATA_SIZE          : natural                   := 32;
    C_DCACHE_BASEADDR    : std_logic_vector(0 to 31) := X"00000000";
    C_DCACHE_HIGHADDR    : std_logic_vector(0 to 31) := X"3FFFFFFF";
    C_ALLOW_DCACHE_WR    : integer                   := 0;
    C_ADDR_TAG_BITS      : natural                   := 9;
    C_CACHELINE_SIZE     : natural                   := 4;
    C_CACHE_BYTE_SIZE    : natural                   := 8*1024;
    C_DCACHE_ALWAYS_USED : integer                   := 0
    );
  port (
    -- global signals
    Clk   : in std_logic;
    Reset : in std_logic;


    Ex_piperun : in boolean;

    -- Local Data Bus signals
    EX_DataBus_Addr         : in std_logic_vector(0 to C_DATA_SIZE-1);
    MEM_DataBus_Addr        : in std_logic_vector(0 to C_DATA_SIZE-1);
    EX_DataBus_Access       : in std_logic;
    MEM_DataBus_Write_Data  : in std_logic_vector(0 to 31);
    EX_DataBus_Write        : in std_logic;
    MEM_DataBus_Byte_Enable : in std_logic_vector(0 to 3);
    EX_Byte_Access          : in boolean;
    EX_Doublet_Access       : in boolean;

    -- DCache outputs
    WB_DCache_Valid_Read_data : out std_logic_vector(0 to 31);
    MEM_DCache_Data_strobe    : out std_logic;
    MEM_DCache_Drop_request   : out std_logic;
    DCache_idle               : out boolean;

    -- DCache Control signals
    EX_DCache_Enable  : in std_logic;
    WB_Fwd            : in std_logic_vector(0 to C_DATA_SIZE-1);
    WB_Write_DCache   : in boolean;
    EX_DCache_Inhibit : in std_logic;

    -- Trace signals
    Trace_Cache_Req : out std_logic;
    Trace_Cache_Hit : out std_logic;

    -- FSL signals
    DCACHE_FSL_IN_Clk     : out std_logic;
    DCACHE_FSL_IN_Read    : out std_logic;
    DCACHE_FSL_IN_Data    : in  std_logic_vector(0 to 31);
    DCACHE_FSL_IN_Control : in  std_logic;
    DCACHE_FSL_IN_Exists  : in  std_logic;

    DCACHE_FSL_OUT_Clk     : out std_logic;
    DCACHE_FSL_OUT_Write   : out std_logic;
    DCACHE_FSL_OUT_Data    : out std_logic_vector(0 to 31);
    DCACHE_FSL_OUT_Control : out std_logic;
    DCACHE_FSL_OUT_Full    : in  std_logic
    );

end entity DCache_gti;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of DCache_gti is

  constant C_LUT6_OPTIMIZED      : boolean := ( C_TARGET = VIRTEX5 );
  
  component RAM_Module is
    generic (
      C_TARGET     : TARGET_FAMILY_TYPE;
      C_DATA_WIDTH : natural range 1 to 32;
      C_ADDR_WIDTH : natural range 1 to 14;
      C_FORCE_BRAM : boolean);
    port (
      -- PORT A
      CLKA      : in  std_logic;
      WEA       : in  std_logic_vector(0 to 3);  -- Assume byte write handling
      ENA       : in  std_logic;
      ADDRA     : in  std_logic_vector(0 to C_ADDR_WIDTH-1);
      DATA_INA  : in  std_logic_vector(0 to C_DATA_WIDTH-1);
      DATA_OUTA : out std_logic_vector(0 to C_DATA_WIDTH-1);
      -- PORT B
      CLKB      : in  std_logic;
      WEB       : in  std_logic_vector(0 to 3);  -- Assume byte write handling
      ENB       : in  std_logic;
      ADDRB     : in  std_logic_vector(0 to C_ADDR_WIDTH-1);
      DATA_INB  : in  std_logic_vector(0 to C_DATA_WIDTH-1);
      DATA_OUTB : out std_logic_vector(0 to C_DATA_WIDTH-1));
  end component RAM_Module;

  component comparator is
    generic (
      C_TARGET    : TARGET_FAMILY_TYPE;
      C_IS_FIRST  : boolean;
      C_SIZE      : natural);
    port (
      Carry_IN  : in  std_logic;
      DI        : in std_logic;
      A         : in  std_logic_vector(0 to C_SIZE-1);
      B         : in  std_logic_vector(0 to C_SIZE-1);
      Carry_OUT : out std_logic);
  end component comparator;

  component carry_and is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_and;

  component carry_or is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_or;

  -----------------------------------------------------------------------------
  -- Function for determine size of various constants
  -----------------------------------------------------------------------------
  function log2(x : natural) return integer is
    variable i : integer := 0;
  begin
    if x = 0 then return 0;
    else
      while 2**i < x loop
        i := i+1;
      end loop;
      return i;
    end if;
  end function log2;

  function Addr_Bits (x, y : std_logic_vector(0 to 31)) return integer is
    variable addr_nor : std_logic_vector(0 to 31);
  begin
    addr_nor := x xor y;
    for i in 0 to 31 loop
      if addr_nor(i) = '1' then return i;
      end if;
    end loop;
    return(32);
  end function Addr_Bits;

  constant C_VALID_ADDR_BITS : integer := Addr_Bits(C_DCACHE_HIGHADDR, C_DCACHE_BASEADDR);

  function calc_addr_tag_bits return natural is
    variable temp : integer;
  begin  -- function calc_addr_tag_bits
    if (C_ADDR_TAG_BITS /= 0) then
      return C_ADDR_TAG_BITS;
    else
      -- The number of needed address tag bits is the full 32 bit address
      -- minus the number of bits of the cache size since it's direct mapped and
      -- minus the number of bits outside the cacheable address range
      temp := 32 - log2(C_CACHE_BYTE_SIZE) - C_VALID_ADDR_BITS;
      if (temp > 0) then
        return temp;
      elsif (temp = 0) then  -- Enforce a tag size of at least 1, otherwise the code breaks
        return 1;
      else
        assert false report "To large data cache for the selected cacheable address range" severity failure;
        return 1;
      end if;
    end if;
  end function calc_addr_tag_bits;

  constant NO_ADDR_TAG_BITS : natural := calc_addr_tag_bits;

  constant Tag_Word_Size   : natural := C_CACHELINE_SIZE + 1 + NO_ADDR_TAG_BITS;
  constant CACHELINE_BITS  : natural := log2(C_CACHELINE_SIZE);
  constant Nr_Of_Tag_Words : natural := (C_CACHE_BYTE_SIZE)/(C_CACHELINE_SIZE*4);
  constant Tag_Addr_Size   : natural := log2(Nr_Of_Tag_Words);
  subtype  TAG_ADDR_TYPE is std_logic_vector(0 to Tag_Addr_Size-1);

  subtype TAG_WORD_TYPE is std_logic_vector(0 to Tag_Word_Size-1);

  constant Nr_Of_Data_Words : natural := (C_CACHE_BYTE_SIZE/4);
  constant Data_Addr_Size   : natural := log2(Nr_Of_Data_Words);
  subtype  DATA_ADDR_TYPE is std_logic_vector(0 to Data_Addr_Size-1);

  -- Always use BRAM for tag if data RAM is >= 2048 bits
  constant Tag_Force_BRAM  : boolean := Data_Addr_Size >= 9;

  signal ex_valid_addr : std_logic;

  signal cache_updated_allowed : std_logic;
  signal xx_access             : std_logic;
  signal xx_valid_data         : std_logic;
  signal xx_data               : std_logic_vector(0 to 31);
  signal mem_valid_req         : std_logic;
  signal mem_valid_req_XX      : std_logic;
  signal mem_write_req         : std_logic;
  signal mem_first_cycle       : std_logic;

  signal mem_cachehit_data : std_logic_vector(0 to C_DATA_SIZE-1);

  signal mem_tag_hit                   : std_logic;
  signal mem_tag_miss                  : std_logic;
  signal mem_cache_hit                 : std_logic;
  signal mem_cache_hit_pending         : std_logic;
  signal mem_cache_hit_pending_delayed : std_logic;
  signal mem_read_cache_hit_direct     : std_logic;
  signal mem_read_cache_hit_posted     : std_logic;
  signal mem_read_cache_hit            : std_logic;
  signal mem_read_cache_miss_i         : std_logic;
  signal mem_read_cache_miss           : std_logic;
  signal mem_read_cache_miss_sel       : std_logic;
  signal mem_write_cache_hit_direct    : std_logic;
  signal mem_write_cache_hit_posted    : std_logic;
  signal mem_write_cache_hit           : std_logic;
  signal mem_write_cache_hit_delayed   : std_logic;
  signal mem_write_cache_miss          : std_logic;
  signal mem_write_cache_miss_delayed  : std_logic;

  signal ex_tag_addr : TAG_ADDR_TYPE;

  signal mem_new_tag_write_i : std_logic_vector(0 to 3);
  signal mem_new_tag_write   : std_logic_vector(0 to 3);
  signal mem_new_tag_bits    : TAG_WORD_TYPE;
  signal mem_new_tag_addr_i  : TAG_ADDR_TYPE;
  signal mem_new_tag_addr    : TAG_ADDR_TYPE;

  constant null_tag_data          : TAG_WORD_TYPE := (others => '0');
  signal   mem_tag_bits           : TAG_WORD_TYPE;
  signal   mem_tag_bits_addr_part : std_logic_vector(0 to NO_ADDR_TAG_BITS);
  signal   Check_tag_addr_part    : std_logic_vector(0 to NO_ADDR_TAG_BITS);

  signal   CacheLine_Cnt      : std_logic_vector(0 to CACHELINE_BITS-1);
  signal   CacheLine_Cnt2     : std_logic_vector(0 to CACHELINE_BITS-1);
  constant CacheLine_Cnt_Low  : std_logic_vector(0 to CACHELINE_BITS-1) := (others => '0');
  constant CacheLine_Cnt_High : std_logic_vector(0 to CACHELINE_BITS-1) := (others => '1');
  signal   Update_Idle        : std_logic;
  signal   delay_update_idle  : std_logic;

  signal cacheline_update_write : std_logic_vector(0 to 3);

  signal Valid_Bits : std_logic_vector(0 to C_CACHELINE_SIZE-1);