barrel_shifter_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      if Clk'event and Clk = '1' then
        if Reset = '1' or not EX_Is_BS_Instr then
          mem_left_shift <= true;
        elsif (EX_PipeRun) then
          mem_left_shift <= EX_Left_Shift;
        end if;
      end if;
    end process MEM_Left_Shift_PROCESS;

    ----------------------------------------
    -- MEM_Void_Bit_PROCESS
    -- MEM stage bit to fill with
    ----------------------------------------
    MEM_Void_Bit_PROCESS: process (Clk) is
    begin -- process MEM_Void_Bit_PROCESS
      if Clk'event and Clk = '1' then
        if Reset = '1' or not EX_Is_BS_Instr then
          mem_void_bit <= '0';
        elsif (EX_PipeRun) then
          mem_void_bit <= ex_void_bit;
        end if;
      end if;
    end process MEM_Void_Bit_PROCESS;

    ----------------------------------------
    -- MEM_Mux4_Rev
    -- Reverse mem_mux4 for right shift
    ----------------------------------------
    MEM_Mux4_Rev : process (mem_mux4) is
       variable rev : DATA_TYPE;
    begin -- process EX_OP1_Rev;
      for I in mem_mux4'left to mem_mux4'right loop
        rev(I) := mem_mux4(mem_mux4'right - I);
      end loop; -- I
      mem_mux4_reverse <= rev;
    end process Mem_Mux4_Rev;

    ----------------------------------------
    -- MEM_Barrel_Result_Mux5_PROCESS
    -- Mux to Select final result
    ----------------------------------------
    MEM_Barrel_Result_Mux5_PROCESS : process (mem_mux4, mem_mux4_reverse, mem_left_shift) is
    begin -- process MEM_Barrel_Result_Mux5_PROCESS
      if (mem_left_shift) then
        MEM_Barrel_Result <= mem_mux4;
      else
        MEM_Barrel_Result <= mem_mux4_reverse;
      end if;
    end process MEM_Barrel_Result_Mux5_PROCESS;
    

    --***************************************************************************
    --***************************************************************************
    --                   Special for LUT4
    --***************************************************************************
    --***************************************************************************
    
    Use_BS_LUT4: if (not C_LUT6_OPTIMIZED) generate
    
      signal ex_sel8_4      : std_logic_vector(0 to 1);
      signal mem_shift16    : std_logic;
      
    begin
  
      --***************************************************************************
      --***************************************************************************
      --                   Execution (EX) stage handling
      --***************************************************************************
      --***************************************************************************
      
      ex_sel8_4 <= EX_BS_Num_Bits(EX_BS_Num_Bits'right-3 to EX_BS_Num_Bits'right-2);
      
      --***************************************************************************
      --***************************************************************************
      --                   Memory (MEM) stage handling
      --***************************************************************************
      --***************************************************************************
  
      ----------------------------------------
      -- MEM_Shift16_PROCESS
      -- MEM stage select 0 or 16 bit shift
      ----------------------------------------
      MEM_Shift16_PROCESS: process (Clk) is
      begin -- process MEM_Shift16_PROCESS
        if Clk'event and Clk = '1' then
          if Reset = '1' or not EX_Is_BS_Instr then
            mem_shift16 <= '0';
          elsif (EX_PipeRun) then
            mem_shift16 <= EX_BS_Num_Bits(EX_BS_Num_Bits'right-4);
          end if;
        end if;
      end process MEM_Shift16_PROCESS;
  
      ----------------------------------------
      -- Zero_Twelve_Bits_Mux3_DFF
      -- This third mux selects between 0, 4, 8, 12 bits shifter
      ----------------------------------------
      Zero_Twelve_Bits_Mux3_DFF : process (Clk) is
      begin -- Zero_Twelve_Bits_Mux3_DFF
        if Clk'event and Clk = '1' then -- rising clock edge
          if Reset = '1' or not EX_Is_BS_Instr then
            mem_mux3 <= (others => '0');
          elsif (EX_PipeRun) then
            if    (ex_sel8_4 = "00") then
              -- No additional shifting from this mux
              mem_mux3 <= ex_mux2;
            elsif (ex_sel8_4 = "01") then
              -- Shift another 4 bits
              mem_mux3 <= (others => ex_void_bit);
              mem_mux3(mem_mux3'left to mem_mux3'right-4)  <= ex_mux2(ex_mux2'left+4 to ex_mux2'right);
            elsif (ex_sel8_4 = "10") then
              -- Shift another 8 bits
              mem_mux3 <= (others => ex_void_bit);
              mem_mux3(mem_mux3'left to mem_mux3'right-8)  <= ex_mux2(ex_mux2'left+8 to ex_mux2'right);
            else --            "11"
              -- Shift another 12 bits
              mem_mux3 <= (others => ex_void_bit);
              mem_mux3(mem_mux3'left to mem_mux3'right-12) <= ex_mux2(ex_mux2'left+12 to ex_mux2'right);
            end if;
          end if;
        end if;
      end process Zero_Twelve_Bits_Mux3_DFF;
  
      ----------------------------------------
      -- Zero_Sixteen_Bits_Mux4
      -- This fourth mux selects between 0 and 16 bits shift
      ----------------------------------------
      Zero_Sixteen_Bits_Mux4 : process (mem_mux3, mem_shift16, mem_void_bit) is
      begin -- process Zero_Sixteen_Bits_Mux4
        if (mem_shift16 = '0') then
          -- no additional shifting
          mem_mux4 <= mem_mux3;
        else -- '1'
          -- shift another 16 bits
          mem_mux4 <= (others => mem_void_bit);
          mem_mux4(mem_mux4'left to mem_mux4'right-16) <= mem_mux3(mem_mux3'left+16 to mem_mux3'right);
        end if;
      end process Zero_Sixteen_Bits_Mux4;
  
    end generate Use_BS_LUT4;
    
    
    --***************************************************************************
    --***************************************************************************
    --                   Special for LUT6
    --***************************************************************************
    --***************************************************************************
    
    Use_BS_LUT6: if (C_LUT6_OPTIMIZED) generate
    
      signal ex_shift4         : std_logic;
      signal mem_shift16_8     : std_logic_vector(0 to 1);
      
    begin
    
      --***************************************************************************
      --***************************************************************************
      --                   Execution (EX) stage handling
      --***************************************************************************
      --***************************************************************************
      
      ex_shift4 <= EX_BS_Num_Bits(EX_BS_Num_Bits'right-2);
      
      
      --***************************************************************************
      --***************************************************************************
      --                   Memory (MEM) stage handling
      --***************************************************************************
      --***************************************************************************
  
      ----------------------------------------
      -- MEM_Shift16_PROCESS
      -- MEM stage select 0 or 16 bit shift
      ----------------------------------------
      MEM_Shift16_8_PROCESS: process (Clk) is
      begin -- process MEM_Shift16_PROCESS
        if Clk'event and Clk = '1' then
          if Reset = '1' or not EX_Is_BS_Instr then
            mem_shift16_8 <= (others=>'0');
          elsif (EX_PipeRun) then
            mem_shift16_8 <= EX_BS_Num_Bits(EX_BS_Num_Bits'right-4 to EX_BS_Num_Bits'right-3);
          end if;
        end if;
      end process MEM_Shift16_8_PROCESS;
  
      ----------------------------------------
      -- Zero_Twelve_Bits_Mux3_DFF
      -- This third mux selects between 0, 4 bits shifter
      ----------------------------------------
      Zero_Four_Bits_Mux3_DFF : process (Clk) is
      begin -- Zero_Twelve_Bits_Mux3_DFF
        if Clk'event and Clk = '1' then -- rising clock edge
          if Reset = '1' or not EX_Is_BS_Instr then
            mem_mux3 <= (others => '0');
          elsif (EX_PipeRun) then
            if (ex_shift4 = '0') then
              -- no additional shifting
              mem_mux3 <= ex_mux2;
            else -- '1'
              -- shift another 16 bits
              mem_mux3 <= (others => ex_void_bit);
              mem_mux3(mem_mux3'left to mem_mux3'right-4) <= ex_mux2(ex_mux2'left+4 to ex_mux2'right);
            end if;
          end if;
        end if;
      end process Zero_Four_Bits_Mux3_DFF;
  
      ----------------------------------------
      -- Zero_Sixteen_Bits_Mux4
      -- This fourth mux selects between 0, 8, 16, 24 bits shifter
      ----------------------------------------
      Zero_Sixteen_Bits_Mux4 : process (mem_mux3, mem_shift16_8, mem_void_bit) is
      begin -- process Zero_Sixteen_Bits_Mux4
        if    (mem_shift16_8 = "00") then
          -- No additional shifting from this mux
          mem_mux4 <= mem_mux3;
        elsif (mem_shift16_8 = "01") then
          -- Shift another 8 bits
          mem_mux4 <= (others => mem_void_bit);
          mem_mux4(mem_mux4'left to mem_mux4'right-8)  <= mem_mux3(mem_mux3'left+8 to mem_mux3'right);
        elsif (mem_shift16_8 = "10") then
          -- Shift another 16 bits
          mem_mux4 <= (others => mem_void_bit);
          mem_mux4(mem_mux4'left to mem_mux4'right-16)  <= mem_mux3(mem_mux3'left+16 to mem_mux3'right);
        else --            "11"
          -- Shift another 24 bits
          mem_mux4 <= (others => mem_void_bit);
          mem_mux4(mem_mux4'left to mem_mux4'right-24) <= mem_mux3(mem_mux3'left+24 to mem_mux3'right);
        end if;
      end process Zero_Sixteen_Bits_Mux4;
      
    end generate Use_BS_LUT6;
    
  end generate Use_HW_BS;

end architecture IMP;