barrel_shifter_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: barrel_shifter_gti.vhd,v 1.2 2007/10/23 11:00:32 stefana Exp $
-------------------------------------------------------------------------------
-- barrel_shifter - entity/architecture
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        barrel_shifter.vhd
-- Version:         v2.00a
-- Description:     Implements a barrel shifter
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              barrel_shifter.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/10/23 11:00:32 $
--
-- History:
--   goran  2001-09-18    First Version
--   BJS    2005-09-13
-- ^^^^^^
--                        Updated for new pipeline
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-- pragma xilinx_rtl_off
library unisim;
use unisim.vcomponents.all;
-- pragma xilinx_rtl_on

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity Barrel_Shifter_gti is
  generic (
    C_TARGET     : TARGET_FAMILY_TYPE;
    C_USE_BARREL : boolean              := false       -- Hardware barrel shifter
  );
  port (
    Clk               : in  std_logic;                 -- Clock
    Reset             : in  std_logic;                 -- Reset
    EX_Op1            : in  DATA_TYPE;                 -- First operand (to be shifted)
    -- EX_Not_Barrel_Op  : in  boolean;                   -- Disable barrel shifter
    EX_Is_BS_Instr    : in  boolean;                   -- If this is an active BS instruction
    EX_Left_Shift     : in  boolean;                   -- Select left/right shift (side)
    EX_Arith_Shift    : in  boolean;                   -- Arithmetic/logical shift (type)
    EX_BS_Num_Bits    : in  BSNUM_TYPE;                -- Number of bits to shift
    EX_PipeRun        : in  boolean;                   -- Move the execute stage
    MEM_Barrel_Result : out DATA_TYPE                  -- Barrel shifter result
  );
end entity Barrel_Shifter_gti;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of Barrel_Shifter_gti is

  constant C_LUT6_OPTIMIZED      : boolean := ( C_TARGET = VIRTEX5 );

begin -- architecture IMP

  -- No hardware barrel shifter
  -- Use software barrel shifter
  No_HW_BS : if (not C_USE_BARREL) generate
    MEM_Barrel_Result <= (others => '0');
  end generate No_HW_BS;

  Use_HW_BS : if (C_USE_BARREL) generate
    -- Reversed Op1 when doing right shift
    signal ex_op1_reverse : DATA_TYPE;
    signal ex_void_bit    : std_logic;
    
    signal ex_sel2_1      : std_logic_vector(0 to 1);

    signal ex_mux1        : DATA_TYPE;
    signal ex_mux2        : DATA_TYPE;

    signal mem_left_shift    : boolean;
    signal mem_void_bit      : std_logic;
    signal mem_mux3          : DATA_TYPE;
    signal mem_mux4          : DATA_TYPE;
    signal mem_mux4_reverse  : DATA_TYPE;
    
  begin
    ----------------------------------------
    -- Overview:
    ----------------------------------------
    -- LUT4:
    -- 1) Reverses Op1 if right shifting (Mux to select between reversed or not)
    -- 2) Mux to select between 0, 1, 2, or 3 bits shifted
    -- 3) Mux to select between 0, 4, 8, or 12 bits shifted (Clocked output)
    -- 4) Mux to select between 0, 16 bits shifted
    -- 5) Reverse 4 if right shifting (Mux to select between reversed or not)
    -- 
    -- LUT6:
    -- 1) Reverses Op1 if right shifting (Mux to select between reversed or not)
    -- 2) Mux to select between 0, 1, 2, or 3 bits shifted
    -- 3) Mux to select between 0, 4 bits shifted (Clocked output)
    -- 4) Mux to select between 0, 8, 16, or 24 bits shifted
    -- 5) Reverse 4 if right shifting (Mux to select between reversed or not)
    ----------------------------------------

    --***************************************************************************
    --***************************************************************************
    --                   Execution (EX) stage handling
    --***************************************************************************
    --***************************************************************************
    
    -- On an arithmetic right shift, shift in the MSb of Op1
    -- Otherwise, shift in zeros
    ex_void_bit <= EX_Op1(0) when (EX_Arith_Shift and (not EX_Left_Shift)) else '0';

    ----------------------------------------
    -- EX_OP1_Rev
    -- Reverse Op1 for right shift
    -- This process requires no logic
    -- It is followed by a mux that selects the reversed or not for right shift
    -- vs. left shift.  So that there is a mux to select between the two at
    -- the beginning and end, but the rest of the logic is the same.
    ----------------------------------------
    EX_OP1_Rev : process (EX_Op1) is
       variable rev : DATA_TYPE;
    begin -- process EX_OP1_Rev;
      for I in EX_Op1'left to EX_Op1'right loop
        rev(I) := EX_Op1(EX_Op1'right - I);
      end loop; -- I
      ex_op1_reverse <= rev;
    end process EX_OP1_Rev;

    -- MUX1 at beginning to select between left and right shift
    -- Reversed Op1 used for right shift
    ex_mux1 <= EX_Op1 when EX_Left_Shift else ex_op1_reverse;

    -- Select the number of bits to shift for the second mux
    ex_sel2_1 <= EX_BS_Num_Bits(EX_BS_Num_Bits'right-1 to EX_BS_Num_Bits'right);

    ----------------------------------------
    -- Zero_Three_Bits_Mux2
    -- This second mux selects between 0, 1, 2, and 3 bits shifted
    ----------------------------------------
    Zero_Three_Bits_Mux2 : process (ex_mux1, ex_sel2_1, ex_void_bit) is
    begin -- process Zero_Three_Bits_Mux2
      if    (ex_sel2_1 = "00") then
        -- No shifting this mux
        ex_mux2 <= ex_mux1;
      elsif (ex_sel2_1 = "01") then
        -- Shift 1 bit
        ex_mux2 <= (others => ex_void_bit);
        ex_mux2(ex_mux2'left to ex_mux2'right-1) <= ex_mux1(ex_mux1'left+1 to ex_mux1'right);
      elsif (ex_sel2_1 = "10") then
        -- Shift 2 bits
        ex_mux2 <= (others => ex_void_bit);
        ex_mux2(ex_mux2'left to ex_mux2'right-2) <= ex_mux1(ex_mux1'left+2 to ex_mux1'right);
      else --          "11"
        -- Shift 3 bits
        ex_mux2 <= (others => ex_void_bit);
        ex_mux2(ex_mux2'left to ex_mux2'right-3) <= ex_mux1(ex_mux1'left+3 to ex_mux1'right);
      end if;
    end process Zero_Three_Bits_Mux2;

  
    --***************************************************************************
    --***************************************************************************
    --                   Memory (MEM) stage handling
    --***************************************************************************
    --***************************************************************************
    
    ----------------------------------------
    -- MEM_Left_Shift_PROCESS
    -- MEM stage left/right shift (side)
    ----------------------------------------
    MEM_Left_Shift_PROCESS: process (Clk) is
    begin -- process MEM_Left_Shift_PROCESS