icache_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

        begin
  
          valid_check_carry_and_I : carry_and
            generic map (C_TARGET => C_TARGET)              -- [TARGET_FAMILY_TYPE]
            port map (Carry_IN  => valid_check_carry(I+1),  -- [in  std_logic]
                      A         => valid_check_sel(I),      -- [in  std_logic]
                      Carry_OUT => valid_check_carry(I));   -- [out std_logic]
  
        end generate valid_check_cacheline;
  
        Word_Is_Valid <= valid_check_carry(0);
      end generate Using_8Line_6LUT;
    end generate Using_8word_lines;

    Using_4word_lines : if (C_CACHELINE_SIZE = 4) generate
    begin
      Using_4Line_4LUT : if ( not C_LUT6_OPTIMIZED ) generate
        signal sel1  : std_logic;
        signal sel2  : std_logic;
        signal carry : std_logic;
      begin
        -- last_valid_instr_tag_addr(28 to 29) = "11" <=> tag_bits(3)
        -- last_valid_instr_tag_addr(28 to 29) = "10" <=> tag_bits(2)
        Sel1 <= not(last_valid_instr_tag_addr(28)) or
                ((last_valid_instr_tag_addr(29) and tag_bits(3)) or
                 (not(last_valid_instr_tag_addr(29)) and tag_bits(2)));
  
        Word_Valid_MUXCY_1 : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => tag_ok,
            S  => Sel1,                       -- [in  std_logic]
            LO => carry);                     -- [out std_logic]
  
        -- last_valid_instr_tag_addr(28 to 29) = "01" <=> tag_bits(1)
        -- last_valid_instr_tag_addr(28 to 29) = "00" <=> tag_bits(0)
        Sel2 <= last_valid_instr_tag_addr(28) or
                ((last_valid_instr_tag_addr(29) and tag_bits(1)) or
                 (not(last_valid_instr_tag_addr(29)) and tag_bits(0)));
  
        Word_Valid_MUXCY_2 : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => carry,
            S  => Sel2,                       -- [in  std_logic]
            LO => word_is_valid);             -- [out std_logic]
  
      end generate Using_4Line_4LUT;
      
      Using_4Line_6LUT : if ( C_LUT6_OPTIMIZED ) generate
        signal sel   : std_logic;
      begin
        -- last_valid_instr_tag_addr(28 to 29) = "11" <=> tag_bits(3)
        -- last_valid_instr_tag_addr(28 to 29) = "10" <=> tag_bits(2)
        -- last_valid_instr_tag_addr(28 to 29) = "01" <=> tag_bits(1)
        -- last_valid_instr_tag_addr(28 to 29) = "00" <=> tag_bits(0)
        Sel  <= tag_bits(3) when (last_valid_instr_tag_addr(28 to 29) = "11") else 
                tag_bits(2) when (last_valid_instr_tag_addr(28 to 29) = "10") else 
                tag_bits(1) when (last_valid_instr_tag_addr(28 to 29) = "01") else 
                tag_bits(0) when (last_valid_instr_tag_addr(28 to 29) = "00") else 
                '0';
        
        Lut6_Word_Valid_MUXCY : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => tag_ok,
            S  => Sel,                        -- [in  std_logic]
            LO => word_is_valid);             -- [out std_logic]
  
      end generate Using_4Line_6LUT;
    end generate Using_4word_lines;

    Using_XX_Access_Part2 : if (C_ICACHE_ALWAYS_USED /= 0) generate
      carry_or_I1 : carry_or
        generic map (
          C_TARGET => C_TARGET)         -- [TARGET_FAMILY_TYPE]
        port map (
          Carry_IN  => word_is_valid,   -- [in  std_logic]
          A         => xx_valid_data,   -- [in  std_logic]
          Carry_OUT => icache_hit);     -- [out std_logic]
    end generate Using_XX_Access_Part2;

    Not_Using_XX_Access_Part2: if (C_ICACHE_ALWAYS_USED = 0) generate
      icache_hit <= word_is_valid;      
    end generate Not_Using_XX_Access_Part2;
    
  end generate Using_FPGA_FSL_2;

  icache_miss <= valid_req_1st_XX and not Tag_ok;

  -----------------------------------------------------------------------------
  -- MCH interface
  -----------------------------------------------------------------------------

  -- XCL Clocks
  ICACHE_FSL_IN_Clk  <= Clk;
  ICACHE_FSL_OUT_Clk <= Clk;

  -- Only request a new cacheline if the address part of the tag doesn't match
  ICACHE_FSL_OUT_Write   <= icache_miss when not reset_bool else '0';
  ICACHE_FSL_OUT_Data    <= instr_Addr_1;
  ICACHE_FSL_OUT_Control <= '0';        -- Only read requests

  -- Always directly consume incoming cacheline data 
  ICACHE_FSL_IN_Read <= ICACHE_FSL_IN_Exists;

  -----------------------------------------------------------------------------
  -- Save the cacheline request address
  -----------------------------------------------------------------------------
  Requested_Address : process (Clk) is
  begin  -- process Requested_Address
    if Clk'event and Clk = '1' then     -- rising clock edge
      if reset_bool then                     -- synchronous reset (active high)
        req_Addr <= (others => '0');
      elsif (icache_miss = '1') then
        req_Addr <= req_Addr_next;
      end if;
    end if;
  end process Requested_Address;

  CacheLine_Counter : process (Clk) is
  begin  -- process CacheLine_Counter
    if Clk'event and Clk = '1' then     -- rising clock edge
      if reset_bool then                     -- synchronous reset (active high)
        cacheline_cnt <= (others => '0');
      elsif (ICACHE_FSL_IN_Exists = '1') then
        cacheline_cnt <= std_logic_vector(unsigned(cacheline_cnt) + 1);
      end if;
    end if;
  end process CacheLine_Counter;

  CacheLine_Counter2 : process (Clk) is
  begin  -- process CacheLine_Counter2
    if Clk'event and Clk = '1' then     -- rising clock edge
      if reset_bool then                     -- synchronous reset (active high)
        cacheline_cnt2 <= (others => '0');
      else
        if (Update_Idle = '1') then
          cacheline_cnt2 <= req_Addr(30 - CACHELINE_BITS to 29);
        elsif (ICACHE_FSL_IN_Exists = '1') then
          cacheline_cnt2 <= std_logic_vector(unsigned(cacheline_cnt2) + 1);
        end if;
      end if;
    end if;
  end process CacheLine_Counter2;

  Update_Idle <= '1' when (cacheline_cnt = cacheline_cnt_Low and ICACHE_FSL_IN_Exists = '0') or
                 (cacheline_cnt = cacheline_cnt_High and ICACHE_FSL_IN_Exists = '1')
                 else '0';

  ICACHE_Idle_DFF : process (Clk) is
  begin  -- process ICACHE_Idle_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset = '1' then            -- synchronous reset (active high)
        ICACHE_Idle <= true;
      else
        ICACHE_Idle <= Update_Idle = '1';
      end if;
    end if;
  end process ICACHE_Idle_DFF;

  -----------------------------------------------------------------------------
  -- Latch the addresses while there is no updating of a new cacheline in progress
  -----------------------------------------------------------------------------
  New_Tag_Addr_DFF : process (Clk) is
  begin  -- process New_Tag_Addr_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Update_Idle = '1' then
        new_tag_addr <= req_Addr(30 - CACHELINE_BITS - Tag_Addr_Size
                                 to 29-CACHELINE_BITS);
        addr_Tag_Bits <= addr_Tag_Bits_next;
      end if;
    end if;
  end process New_Tag_Addr_DFF;

  -- Calculate the valid bits that will be written during a cacheline update
  Valid_Bits_Handle : process (Clk) is
    variable tmp : std_logic_vector(valid_Bits'range);
  begin  -- process Valid_Bits_Handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Update_Idle = '1' then         -- synchronous reset (active high)
        valid_Bits                                                          <= (others => '0');
        valid_Bits(to_integer(unsigned(req_Addr(30-CACHELINE_BITS to 29)))) <= '1';
      elsif (ICACHE_FSL_IN_Exists = '1') then
        tmp(1 to tmp'right) := valid_Bits(0 to valid_Bits'right-1);
        tmp(0)              := valid_Bits(valid_Bits'right);
        valid_Bits          <= tmp or valid_Bits;
      end if;
    end if;
  end process Valid_Bits_Handle;

  -- Calculate the whole tag during updates
  New_Tag_Bits_Gen : process(ICACHE_FSL_IN_Exists, real_valid_bits, addr_Tag_Bits) is
  begin  -- process New_Tag_Bits_Gen
    new_tag_bits <= (others => '0');
    if ICACHE_FSL_IN_Exists = '1' then
      new_tag_bits(C_CACHELINE_SIZE) <= '1';  -- Always write in a valid tag        
    else
      new_tag_bits(C_CACHELINE_SIZE) <= '0';
    end if;
    new_tag_bits(0 to C_CACHELINE_SIZE-1)                                     <= real_valid_bits;
    new_tag_bits(1 + C_CACHELINE_SIZE to C_CACHELINE_SIZE + NO_ADDR_TAG_BITS) <= addr_Tag_Bits;
  end process New_Tag_Bits_Gen;

  data_write_cache <= (others => '1') when (ICACHE_FSL_IN_Exists = '1') and (cache_updated_allowed = '1') else (others => '0');
  tag_write_cache  <= (others => '1') when (Write_ICache) or ( (ICACHE_FSL_IN_Exists = '1') and (cache_updated_allowed = '1')) else (others => '0');

  real_valid_bits <= valid_Bits when ICACHE_FSL_IN_Exists = '1' else All_False_Bits;

  real_new_tag_addr <= new_tag_addr when ICACHE_FSL_IN_Exists = '1' else
                       WB_fwd(30 - CACHELINE_BITS - Tag_Addr_Size
                           to 29-CACHELINE_BITS);
  ---------------------------------------------------------------------------
  -- The tag memory
  ---------------------------------------------------------------------------
  tag_addr_lookup <= valid_instr_tag_addr(30 - CACHELINE_BITS - Tag_Addr_Size
                                          to 29-CACHELINE_BITS);

  Tag_RAM_Module : RAM_Module
    generic map (
      C_TARGET     => C_TARGET,
      C_DATA_WIDTH => Tag_Word_Size,    -- [natural range 1 to 36]
      C_ADDR_WIDTH => Tag_Addr_Size,    -- [natural range 1 to 14]
      C_FORCE_BRAM => Tag_Force_BRAM)   -- [boolean]
    port map (
      -- PORT A
      CLKA      => Clk,                 -- [in  std_logic]
      WEA       => null4,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
--      ENA       => '1',                 -- [in  std_logic]
      ENA       => ram_enable,                 -- [in  std_logic]
      ADDRA     => tag_addr_lookup,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INA  => null_tag_word,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTA => tag_bits,     -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]
      -- PORT B
      CLKB      => clk,                 -- [in  std_logic]
      WEB       => tag_write_cache,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
      ENB       => '1',                 -- [in  std_logic]
      ADDRB     => real_new_tag_addr,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INB  => new_tag_bits,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTB => open);        -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]
  
  ---------------------------------------------------------------------------
  -- The Data memory
  ---------------------------------------------------------------------------

  New_Data_Addr_DFF : process (Clk) is
  begin  -- process New_Data_Addr_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Update_Idle = '1' then
        New_Data_Addr1 <= req_Addr(30-Data_Addr_Size to 29-CACHELINE_BITS);
      end if;
    end if;
  end process New_Data_Addr_DFF;

  New_Data_Addr <= New_Data_Addr1 & Cacheline_Cnt2;

  data_addr_lookup <= valid_instr_tag_addr(30-Data_Addr_Size to 29);

  Data_RAM_Module : RAM_Module
    generic map (
      C_TARGET     => C_TARGET,
      C_DATA_WIDTH => C_DATA_SIZE,      -- [natural range 1 to 36]
      C_ADDR_WIDTH => Data_Addr_Size,   -- [natural range 1 to 14]
      C_FORCE_BRAM => false)            -- [boolean]
    port map (
      -- PORT A
      CLKA      => Clk,                 -- [in  std_logic]
      WEA       => null4,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
--      ENA       => '1',                 -- [in  std_logic]
      ENA       => ram_enable,                 -- [in  std_logic]
      ADDRA     => data_addr_lookup,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INA  => null32,       -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTA => iCACHE_Data_i,  -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]
      -- PORT B
      CLKB      => Clk,                 -- [in  std_logic]
      WEB       => data_write_cache,  -- [in  std_logic_vector(0 to 3)] Assume byte write handling
      ENB       => '1',                 -- [in  std_logic]
      ADDRB     => New_Data_Addr,  -- [in  std_logic_vector(0 to C_ADDR_WIDTH-1)]
      DATA_INB  => ICACHE_FSL_IN_Data,  -- [in  std_logic_vector(0 to C_DATA_WIDTH-1)]
      DATA_OUTB => open);        -- [out std_logic_vector(0 to C_DATA_WIDTH-1)]

  ICACHE_Data <= iCACHE_Data_i when xx_valid_data = '0' else xx_data;
  
  ram_enable <= '1';--(not cacheline_tag_hit) and IB_Addr_Strobe;

end architecture IMP;