zero_detect.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: zero_detect.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Zero Detect - entity/architecture 
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        zero_detect.vhd
-- Version:         v1.00a
-- Description:     Detect if a std_logic_vector signal is zero
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              zero_detect.vhd
--                      -- MUXCY_L  (Xilinx primitive)
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Zero_Detect is
  generic (
    -- Size generics
    C_DATA_SIZE : natural range 4 to 64 := 32;
    C_TARGET    : TARGET_FAMILY_TYPE
    );
  port (
    -- Zero flag signals
    Reg_Test_Equal   : in  std_logic;
    Reg_Test_Equal_N : in  std_logic;
    EX_Result        : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Reg_zero         : out std_logic
    );

end entity Zero_Detect;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

library Unisim;
use Unisim.vcomponents.all;

architecture IMP of Zero_Detect is

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

  constant C_BITS_PER_LUT : integer:= Family_To_LUT_Size(C_TARGET);

begin  -- IMP

  -----------------------------------------------------------------------------
  -- Handles Zero flag
  -----------------------------------------------------------------------------

  Using_FPGA : if (C_TARGET /= RTL) generate
    
    constant DATA_SIZE            : natural := EX_Result'length;
    constant NR_OF_NIBBLES        : natural := (DATA_SIZE+C_BITS_PER_LUT-1)/C_BITS_PER_LUT;
    
    signal   EX_Result_I          : std_logic_vector(0 to NR_OF_NIBBLES * C_BITS_PER_LUT -1);
    signal   nibble_Zero          : std_logic_vector(NR_OF_NIBBLES-1 downto 0);
    signal   zero_CI              : std_logic_vector(NR_OF_NIBBLES downto 0);
    signal   zero_C               : std_logic;      
    
  begin
      
    Part_Of_Zero_Carry_Start : MUXCY_L
      port map (
        DI => '0',                    -- [in  std_logic]
        CI => '1',                    -- [in  std_logic]
        S  => Reg_test_Equal,         -- [in  std_logic]
        LO => zero_CI(0));            -- [out std_logic]

    zero_C <= Reg_Test_Equal_N;

    -- Expand with zero bits if necessary.
    Expand_Bus: process(EX_Result) is
    begin  -- process assign_sigs
      EX_Result_I                   <= (others => '0');
      EX_Result_I(0 to DATA_SIZE-1) <= EX_Result;
    end process Expand_Bus;
    
    -- Detect Zero in carry chain.
    Zero_Detecting : for I in 0 to NR_OF_NIBBLES-1 generate
    begin
      -- Combine the signals that fit into one LUT.
      Compare_All_Bits: process(EX_Result_I)
        variable sel_I   : std_logic;
      begin
        sel_I  :=  '0';
        Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
          sel_I  := sel_I or EX_Result_I(NR_OF_NIBBLES * C_BITS_PER_LUT - I*C_BITS_PER_LUT - C_BITS_PER_LUT + J);
        end loop Compare_Bits;
        nibble_Zero(I) <= not sel_I;
      end process Compare_All_Bits;
      
      I_Part_Of_Zero_Detect : MUXCY_L
        port map (
          DI => zero_C,               -- [in  std_logic]
          CI => zero_CI(I),           -- [in  std_logic]
          S  => nibble_Zero(I),       -- [in  std_logic]
          LO => zero_CI(I+1));        -- [out std_logic]

    end generate Zero_Detecting;
    
    Reg_zero <= zero_CI(NR_OF_NIBBLES);

  end generate Using_FPGA;

  Using_RTL: if (C_TARGET = RTL) generate
    Detect_Zero: process (EX_Result, Reg_Test_Equal, Reg_Test_Equal_N) is
      constant Zero : std_logic_vector(EX_Result'range) := (others => '0');
    begin  -- process Detect_Zero
      if (EX_Result = Zero) then
        Reg_zero <= Reg_Test_Equal;
      else
        Reg_zero <= Reg_Test_Equal_N;
      end if;
    end process Detect_Zero;
  end generate Using_RTL;

end architecture IMP;