mmu.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: mmu.vhd,v 1.3.2.1 2008/01/30 13:38:03 stefana Exp $
-------------------------------------------------------------------------------
-- mmu.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2007 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
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--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        mmu.vhd
--
-- Description:     This file contains an implementation of a Memory Management
--                  Unit based on the Power PC 40x definition.
--
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              mmu.vhd
--                mmu_utlb.vhd
--                  mmu_utlb_ram.vhd
--                mmu_tlb.vhd
--
-------------------------------------------------------------------------------
-- Author:          stefana
-- Revision:        $Revision: 1.3.2.1 $
-- Date:            $Date: 2008/01/30 13:38:03 $
--
-- History:
--   stefana 2006-10-23    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- pragma xilinx_rtl_off
library unisim;
use unisim.vcomponents.all;
-- pragma xilinx_rtl_on
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
use Microblaze_v7_10_a.MMU_Types.all;

entity MMU is
  generic (
    C_TARGET        : TARGET_FAMILY_TYPE;
    C_USE_MMU       : integer := 0;    -- Which MMU mode None=0, Usermode=1,
                                       -- Protect=2, Virtual=3
    C_MMU_DTLB_SIZE : integer := 8;
    C_MMU_ITLB_SIZE : integer := 4;
    C_MMU_TLB_READ  : boolean := true;
    C_MMU_TLB_WRITE : boolean := true;
    C_MMU_ZONES     : integer := 16
  );
  port (
    Clk                      : in  std_logic;
    Reset                    : in  std_logic;

    -- Virtual addresses
    IB_VMode                 : in  std_logic;
    IB_UMode                 : in  std_logic;
    IB_Addr                  : in  std_logic_vector(0 to 31);
    IB_Addr_Strobe           : in  std_logic;    
    IB_Fetch                 : in  std_logic;
    EX_VMode                 : in  std_logic;
    EX_UMode                 : in  std_logic;
    EX_DataBus_Addr          : in  std_logic_vector(0 to 31);
    EX_DataBus_Access        : in  std_logic;
    EX_DataBus_Write         : in  std_logic;
    ICACHE_Drop_Request      : in  std_logic;
    ICACHE_Req_Prev          : in  std_logic;
    ICACHE_Valid_Addr        : in  std_logic;

    -- Register access
    OF_PipeRun               : in  boolean;
    EX_MTS_PID               : in  std_logic;
    EX_MTS_ZPR               : in  std_logic;
    EX_MTS_TLBX              : in  std_logic;
    EX_MTS_TLBLO             : in  std_logic;
    EX_MTS_TLBHI             : in  std_logic;
    EX_MTS_TLBSX             : in  std_logic;
    EX_Op1                   : in  DATA_TYPE;
    EX_PipeRun               : in  boolean;
    EX_Sel_SPR_TLBLO         : in  boolean;
    EX_Sel_SPR_TLBHI         : in  boolean;
    MEM_Sel_SPR_PID          : in  boolean;
    MEM_Sel_SPR_ZPR          : in  boolean;
    MEM_Sel_SPR_TLBX         : in  boolean;
    MEM_Sel_SPR_TLBLO        : in  boolean;
    MEM_Sel_SPR_TLBHI        : in  boolean;
    MEM_PipeRun              : in  boolean;
    EX_DataBus_Access_MMU    : out std_logic;
    WB_Sel_MMU_Res           : out boolean;
    WB_MMU_Result            : out DATA_TYPE;

    IB_Addr_MMU              : out std_logic_vector(0 to 31);
    IB_Addr_Strobe_MMU       : out std_logic;
    IB_Addr_Strobe_LMB_MMU   : out std_logic;
    IB_Fetch_MMU             : out std_logic;
    IB_TLB_Addr_MMU          : out std_logic_vector(0 to 31);
    IB_TLB_Addr_Strobe       : out std_logic;
    IB_Block_Ready_MMU       : out std_logic;
    IB_Cache_Addr_MMU        : out std_logic_vector(0 to 31);
    IB_Valid_TLB_Addr        : out std_logic;
    IF_ICache_Inhibit        : out std_logic;
    MEM_PID                  : out std_logic_vector(0 to 7);

    EX_DataBus_Addr_MMU      : out std_logic_vector(0 to 31);
    EX_DCache_Inhibit        : out std_logic;

    IF_Instr_TLB_Miss_Excep  : out std_logic;
    IF_Instr_Storage_Excep   : out std_logic;
    EX_Data_TLB_Miss_Excep   : out std_logic;
    EX_Data_Storage_Excep    : out std_logic;
    EX_MMU_Stall             : out boolean;
    WB_Zone_Protect          : out std_logic;
    WB_PID                   : out std_logic_vector(24 to 31)
  );
end entity MMU;

library IEEE;
use IEEE.numeric_std.all;

architecture IMP of MMU is

  component MMU_UTLB
    generic (
      C_TARGET        : TARGET_FAMILY_TYPE;
      C_MMU_TLB_WRITE : boolean := true
    );
    port (
      Clk           : in  std_logic;
      Reset         : in  std_logic;

      IVAddr        : in  TAG_TYPE;
      IValid        : in  std_logic;
      IVMode        : in  std_logic;

      DVAddr        : in  TAG_TYPE;
      DValid        : in  std_logic;
      DVMode        : in  std_logic;

      PID           : in  TID_TYPE;

      RegAddr       : in  TLB_Index_Type;
      RegData       : in  DATA_TYPE;
      RegDataLowIn  : in  std_logic_vector(0 to 3);
      RegRdLo       : in  boolean;
      RegRdHi       : in  boolean;
      RegWrLo       : in  std_logic;
      RegWrHi       : in  std_logic;
      RegWrSx       : in  std_logic;

      SizeMask      : out SIZE_Addr_Type;
      MaskedData    : out TLBHI_Type;
      DataHigh      : out TLBHI_Type;
      DataLow       : out DATA_TYPE;
      RegDataLowOut : out std_logic_vector(0 to 3);

      IDataBusy     : out std_logic;
      DDataBusy     : out std_logic;
      RDataBusy     : out std_logic;
      IDataRdy      : out std_logic;
      DDataRdy      : out std_logic;
      RDataRdy      : out std_logic;
      Hit           : out std_logic;
      HitIndex      : out TLB_INDEX_Type;

      EX_MMU_Stall  : out boolean
    );
  end component MMU_UTLB;

  component MMU_TLB is
    generic (
      C_TARGET      : TARGET_FAMILY_TYPE;
      C_TLBHI_WIDTH : natural := 35;
      C_ADDR_WIDTH  : natural range 0 to 3;
      C_STORE_TID   : boolean := true;
      C_STORE_EX    : boolean := true;
      C_STORE_WR    : boolean := true;
      C_MMU_ZONES   : integer := 16;
      C_STORE_G     : boolean := true
    );
    port (
      Clk        : in  std_logic;
      EN         : in  std_logic;

      TLB_Inval  : in  boolean;
      TLB_ADDR   : in  natural;
      TLBLO_WE   : in  std_logic;
      TLBLO_IN   : in  DATA_TYPE;
      TLBHI_WE   : in  std_logic;
      TLBHI_IN   : in  std_logic_vector(0 to C_TLBHI_WIDTH-1);

      DATA_ADDR  : in  std_logic_vector(0 to C_TLBHI_WIDTH - 5);
      HIT_EN     : in  std_logic;
      SIZE_OUT   : out SIZE_Type;
      DATALO_OUT : out DATA_TYPE;
      DATA_HIT   : out std_logic
    );
  end component MMU_TLB;


  constant C_STORE_TID   : boolean := false; -- No TID in shadow TLB
  constant C_STORE_PROT  : boolean := true;  -- Save protect bits in shadow TLB
  constant C_USE_GUARDED : boolean := false; -- Do not implement guarded bit
  constant C_STORE_VALID : boolean := C_USE_MMU = C_MMU_VIRTUAL;

  constant ITLB_WIDTH   : integer := log2(C_MMU_ITLB_SIZE);
  constant DTLB_WIDTH   : integer := log2(C_MMU_DTLB_SIZE);

  subtype Zone_Type     is std_logic_vector(0 to 1);
  type Zone_Vector_Type is array (natural range <>) of Zone_Type;

  signal RegWrLo                   : std_logic;
  signal RegWrHi                   : std_logic;
  signal RegWrSx                   : std_logic;

  signal ex_databus_write_q        : std_logic;

  signal utlb_IValid               : std_logic;
  signal utlb_DValid               : std_logic;
  signal utlb_Hit                  : std_logic;
  signal utlb_HitIndex             : TLB_Index_Type;
  signal RegDataLowIn              : std_logic_vector(0 to 3);
  signal RegDataLowOut             : std_logic_vector(0 to 3);

  signal tlb_Inval                 : boolean;
  signal itlb_Inval                : boolean;
  signal dtlb_Inval                : boolean;

  signal itlb_Addr                 : natural;
  signal dtlb_Addr                 : natural;

  signal itlb_WE                   : std_logic;
  signal dtlb_WE                   : std_logic;

  signal IDATA_HIT                 : std_logic;
  signal IDATA_HIT_EN              : std_logic;
  signal DDATA_HIT                 : std_logic;
  signal DDATA_HIT_EN              : std_logic;

  signal MaskedData                : TLBHI_Type;
  signal DataHigh                  : TLBHI_Type;
  signal DataLow                   : DATA_TYPE;

  signal iDataBusy                 : std_logic;
  signal dDataBusy                 : std_logic;
  signal rDataBusy                 : std_logic;

  signal iDataRdy                  : std_logic;
  signal dDataRdy                  : std_logic;
  signal rDataRdy                  : std_logic;

  signal ex_access_stall           : rboolean;
  signal ex_MMU_Stall_i            : rboolean;
  signal ex_MMU_Stall_UTLB         : boolean;
  signal ex_stall_cycle            : std_logic;
  signal ex_stall_cycle_q          : std_logic;
  signal wb_Sel_MMU_Res_i          : rboolean;

  signal ISIZE_OUT                 : SIZE_Type;
  signal IDATALO_OUT               : DATA_TYPE;
  signal DSIZE_OUT                 : SIZE_Type;
  signal DDATALO_OUT               : DATA_TYPE;

  signal ITLBHi_In                 : std_logic_vector(0 to 33);
  signal ITLBLo_In                 : DATA_TYPE;
  signal DTLBHi_In                 : std_logic_vector(0 to 33);

  signal IData_Addr                : std_logic_vector(0 to 29);
  signal DData_Addr                : std_logic_vector(0 to 29);

  signal mem_pid_i                 : std_logic_vector(24 to 31);
  signal wb_pid_i                  : std_logic_vector(24 to 31);
  signal mem_zpr                   : Zone_Vector_Type(0  to 15);
  signal mem_tlbx                  : std_logic_vector(25 to 31);
  signal TLBX_Low                  : std_logic_vector(26 to 31);

  signal DataLow_ZSEL_Q            : ZSEL_Type;
  signal DataLow_EX_Q              : std_logic;
  signal DataLow_WR_Q              : std_logic;
  signal DataLow_I_Q               : std_logic;
  signal DataLow_G_Q               : std_logic;
  signal utlb_Hit_Q                : std_logic;
  signal UZIndex                   : integer range 0 to 15;
  signal UZIndex_Q                 : integer range 0 to 15;
  signal UZPR_Q                    : std_logic_vector(0 to 1);
  signal iDataRdy_Q                : std_logic;
  signal dDataRdy_Q                : std_logic;

  signal IDATALO_ZSEL_Q            : ZSEL_Type;
  signal IDATALO_EX_Q              : std_logic;
  signal IDATALO_G_Q               : std_logic;
  signal IDATA_HIT_Q               : std_logic;
  signal IZIndex_Q                 : integer range 0 to 15;
  signal IZone                     : Zone_Type;
  signal IEx                       : std_logic;
  signal IG                        : std_logic;
  signal IValid                    : std_logic;
  signal I_UM                      : std_logic;
  signal if_Instr_Storage_Excep_i  : std_logic;

  signal DZPR_Q                    : std_logic_vector(0 to 1);
  signal DDATALO_WR_Q              : std_logic;
  signal DDATALO_I_Q               : std_logic;
  signal DDATA_HIT_Q               : std_logic;
  signal DZIndex                   : integer range 0 to 15;
  signal DZone                     : Zone_Type;
  signal DWr                       : std_logic;
  signal NoWr                      : boolean;
  signal DValid                    : std_logic;
  signal D_UM                      : std_logic;
  signal ex_Data_Storage_Excep_i   : std_logic;
  signal wb_Zone_Protect_i         : std_logic;

  signal IB_Addr_1                 : std_logic_vector(0 to 31);
  signal IB_Addr_strobe_1          : std_logic;
  signal IB_Fetch_1                : std_logic;
  signal ib_tlb_addr_mmu_i         : std_logic_vector(0 to 31);