alu.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: alu.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- alu -  entity/architecture
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        alu.vhd
-- Version:         v2.00a
-- Description:     Implements the ALU functionality which performs the
--                  add/rsub instructions
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              alu.vhd
--                 -- alu_bit.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-- pragma xilinx_rtl_off
library unisim;
use unisim.vcomponents.all;
-- pragma xilinx_rtl_on

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
--    C_AREA_OPTIMIZED        -- Ifthe MB is area optimized or not.
--    C_TARGET                -- Device family
--    C_U_SET                 -- Name of unit
--
-- Definition of Ports:
--
--    EX_ALU_Op               -- Which ALU operation to perform
--    EX_Unsigned_Op          -- Perform unsigned operation (rather than signed)
--
--    EX_CarryIn              -- CarryIn bit (from MSR or forwarding logic)
--    EX_Op1                  -- Operand 1 in EX stage
--    EX_Op2                  -- Operand 2 in EX stage
--
--    EX_ALU_Result           -- Output from ALU
--    EX_ALU_Carry            -- Carry out bit
--
-------------------------------------------------------------------------------
entity ALU is
  generic (
    C_AREA_OPTIMIZED       : integer                := 0;
    C_TARGET : TARGET_FAMILY_TYPE := RTL
  );
  port (
    EX_ALU_Op      : in ALU_OP_TYPE;
    EX_CMP_Op      : in boolean;
    EX_Unsigned_Op : in boolean;
    EX_Use_Carry   : in boolean;

    EX_CarryIn : in std_logic;
    EX_Op1     : in DATA_TYPE;
    EX_Op2     : in DATA_TYPE;

    EX_ALU_Result : out DATA_TYPE;
    EX_ALU_Carry  : out std_logic
  );
end entity ALU;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of ALU is

  component ALU_Bit is
    generic (
      C_TARGET   : TARGET_FAMILY_TYPE;
      C_LAST_BIT : boolean);
    port (
      EX_Op1         : in  std_logic;
      EX_Op2         : in  std_logic;
      EX_ALU_Op      : in  std_logic_vector(0 to 1);
      EX_CarryIn     : in  std_logic;
      EX_CMP_Op      : in  boolean;
      EX_Unsigned_Op : in  boolean;
      EX_Result      : out std_logic;
      EX_CarryOut    : out std_logic);
  end component ALU_Bit;
  
begin

  FPGA_Target : if (C_TARGET /= RTL) generate
    signal ex_subtract_op    : std_logic;
    signal select_carry_in   : std_logic;
    signal alu_carry         : std_logic_vector(0 to DATA_TYPE'right+1);
    signal ex_Use_Carry_stdl : std_logic;
  begin

    ---------------------------------------------------------------------------
    -- Calculate the carry in
    ---------------------------------------------------------------------------

    No_Carry_Decoding: if ( C_AREA_OPTIMIZED /= 0 ) generate
    begin
      alu_carry(DATA_TYPE'right+1)  <= EX_CarryIn;
    end generate No_Carry_Decoding;
  
    Use_Carry_Decoding: if ( C_AREA_OPTIMIZED = 0 ) generate
    begin
      ex_Use_Carry_stdl <= '1' when EX_Use_Carry else '0';
      
      -- select_carry_in <= ex_Use_Carry_stdl
      -- but EX_ALU_Op is needed since it uses the MULT_AND which uses the same
      -- inputs I0 and I1 as the LUT
      alu_carry_select_LUT : LUT3
        generic map(
          INIT => X"F0"
          )
        port map (
          O  => select_carry_in,             -- [out]
          I0 => EX_ALU_Op(EX_ALU_Op'left),   -- [in]
          I1 => EX_ALU_Op(EX_ALU_Op'right),  -- [in]
          I2 => ex_Use_Carry_stdl);          -- [in]

      MULT_AND_I : MULT_AND
        port map (
          I0 => EX_ALU_Op(EX_ALU_Op'left),   -- [in]
          I1 => EX_ALU_Op(EX_ALU_Op'right),  -- [in]
          LO => ex_subtract_op);             -- [out]

      CarryIn_MUXCY : MUXCY_L
        port map (
          DI => ex_subtract_op,                 -- [in  std_logic]
          CI => EX_CarryIn,                     -- [in  std_logic]
          S  => select_carry_in,                -- [in  std_logic]
          LO => alu_carry(DATA_TYPE'right+1));  -- [out std_logic]
    end generate Use_Carry_Decoding;
        
    ALL_Bits : for I in DATA_TYPE'right downto DATA_TYPE'left generate
      ALU_Bit_I1 : ALU_Bit
        generic map (
          C_TARGET   => C_TARGET,            -- [TARGET_FAMILY_TYPE]
          C_LAST_BIT => (I = 0))             -- [boolean]
        port map (
          EX_Op1         => EX_Op1(I),       -- [in  std_logic]
          EX_Op2         => EX_Op2(I),       -- [in  std_logic]
          EX_ALU_Op      => EX_ALU_Op,       -- [in  std_logic_vector(0 to 1)]
          EX_CarryIn     => alu_carry(I+1),  -- [in  std_logic]
          EX_CMP_Op      => EX_CMP_Op, 
          EX_Unsigned_Op => EX_Unsigned_Op,  -- [in  boolean]
          EX_Result      => EX_ALU_Result(I),    -- [out std_logic]
          EX_CarryOut    => alu_carry(I));   -- [out std_logic]
    end generate ALL_Bits;

    EX_ALU_Carry <= alu_carry(0);
    
  end generate FPGA_Target;


  RTL_Target : if (C_TARGET = RTL) generate
    signal carry_res_i   : std_logic_vector(0 to DATA_TYPE'right+1);
    signal alu_op_res    : DATA_TYPE;
    signal alu_result_i  : DATA_TYPE;
    signal arith_carryin : std_logic;
  begin
    -- carry bit selection for subtraction
    arith_carryin <= EX_CarryIn when (EX_Use_Carry  or ( C_AREA_OPTIMIZED /= 0 ) ) else
                     '1' when (EX_ALU_Op = ALU_OP_MINUS) else
                     '0';

    ----------------------------------------
    -- Carry_Res_PROCESS
    -- Handles carry bit
    ----------------------------------------
    Carry_Res_PROCESS : process (EX_ALU_Op, EX_Op1, EX_Op2, arith_carryin) is
      variable op1_i   : std_logic_vector(0 to DATA_TYPE'right+1);
      variable op2_i   : std_logic_vector(0 to DATA_TYPE'right+1);
      variable C       : std_logic_vector(0 to 0);
      variable carry_I : natural range 0 to 1;
    begin
      C(0)  := arith_carryin;
      op1_i := '0' & EX_Op1;
      op2_i := '0' & EX_Op2;

      if (EX_ALU_Op = ALU_OP_PLUS) then
        carry_I := to_integer(unsigned(C));
        carry_res_i <= std_logic_vector(unsigned(op1_i) + unsigned(op2_i) +
                                        carry_I);
      else                              -- ALU_OP_MINUS
        carry_I := to_integer(unsigned(not(C)));
        carry_res_i <= std_logic_vector(unsigned(op2_i) - unsigned(op1_i) -
                                        carry_I);
      end if;
    end process Carry_Res_PROCESS;

    ----------------------------------------
    -- ALU_Op_Res_PROCESS
    -- Mux the ALU operation
    ----------------------------------------
    ALU_Op_Res_PROCESS : process (EX_ALU_Op, EX_Op1, EX_Op2, carry_res_i) is
      variable res_i : std_logic_vector(0 to DATA_TYPE'right+1);
    begin
      case EX_ALU_Op is
        when ALU_OP_OP1 =>              -- "00" Res = Op1
          alu_op_res <= EX_Op1;
        when ALU_OP_OP2 =>              -- "01" Res = Op2
          alu_op_res <= EX_Op2;
        when ALU_OP_PLUS =>             -- "10" Res = Op1 + Op2
          alu_op_res <= carry_res_i(carry_res_i'left + 1 to carry_res_i'right);
        when ALU_OP_MINUS =>  -- "11" Res = Op2 - Op1 = Op2 + ~Op1 + 1
          alu_op_res <= carry_res_i(carry_res_i'left + 1 to carry_res_i'right);
        when others => null;
      end case;
    end process ALU_Op_Res_PROCESS;

    ----------------------------------------
    -- ALU_Carry_PROCESS
    -- Mux the carry bit
    ----------------------------------------
    ALU_Carry_PROCESS : process (EX_ALU_Op, carry_res_i) is
    begin
      -- Carry bit is normally '0'
      EX_ALU_Carry <= '0';

      case EX_ALU_Op is
        when ALU_OP_PLUS =>             -- "10" Res = Op1 + Op2
          EX_ALU_Carry <= carry_res_i(carry_res_i'left);
        when ALU_OP_MINUS =>  -- "11" Res = Op2 - Op1 = Op2 + ~Op1 + 1
          EX_ALU_Carry <= not carry_res_i(carry_res_i'left);
        when others => null;
      end case;
    end process ALU_Carry_PROCESS;

    ----------------------------------------
    -- Compare_PROCESS
    -- Mux for compare result
    -- Handle the sign bit
    ----------------------------------------
    Compare_PROCESS : process (alu_op_res, EX_Unsigned_Op, EX_Op1, EX_Op2) is
    begin
      alu_result_i <= alu_op_res;

      -- A signed compare is the same as an RSUBK. If unsigned and the operands have
      -- same MSb then output of the signed ALU operation is correct, if not then the
      -- result should have the inverse sign of the Op2 MSb
      if EX_CMP_Op and ((EX_Op2(0) xor EX_Op1(0)) = '1') then
        if (EX_Unsigned_Op) then
          alu_result_i(0) <= not EX_Op2(0);
        else
          alu_result_i(0) <= EX_Op2(0);
        end if;
        
      end if;

    end process Compare_PROCESS;

    EX_ALU_Result <= alu_result_i;
  end generate RTL_Target;
  
end architecture IMP;