operand_select.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: operand_select.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Operand_Select - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        operand_select.vhd
-- Version:         v1.00a
-- Description:     Selects which operands to be used for the instruction
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              operand_select.vhd
--                    -- operand_select_bit.vhd
--                              -- LUT3  (Xilinx Primitive)
--                              -- LUT4  (Xilinx Primitive)
--                              -- MUXF5 (Xilinx Primitive)
--                              -- FDCE  (Xilinx Primitive)
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Operand_Select is
  generic (
    -- Size generics
    C_DATA_SIZE      : natural range 4 to 64 := 32;
    C_DEBUG_ENABLED  : integer               := 0;
    C_PVR            : integer               := 0;
    C_FSL_EXCEPTION  : boolean               := false;
    C_USE_EXCEPTIONS : boolean               := true;
    C_USE_FPU_bool   : boolean               := false;
    C_TARGET         : TARGET_FAMILY_TYPE;
    C_INTERRUPT_ADDR : string                := "00000010";
    C_EXT_BRK_ADDR   : string                := "00000018";
    C_EXCEPTION_ADDR : string                := "00000020"
    );
  port (
    Clk   : in std_logic;
    Reset : in boolean;

    OF_PipeRun : in boolean;

    Reg1_Data : in std_logic_vector(0 to C_DATA_SIZE-1);
    Reg2_Data : in std_logic_vector(0 to C_DATA_SIZE-1);
    Imm_Value : in std_logic_vector(0 to 15);
    MSR       : in MSR_REG_TYPE;
    PC_OF     : in std_logic_vector(0 to C_DATA_SIZE-1);
    EX_Result : in std_logic_vector(0 to C_DATA_SIZE-1);

    OpSel1_PC      : in boolean;
    OpSel1_SPR     : in boolean;
    OpSel2_Imm     : in boolean;
    Take_Ext_BRK   : in boolean;
    Take_Exception : in boolean;
    Take_Interrupt : in boolean;
    Store_PC_For_Intr      : in boolean;
    Store_PC_For_Intr_NoImm: in boolean;
    Res_Forward1   : in boolean;
    Res_Forward2   : in boolean;
    Imm_Instr      : in boolean;
    Use_Imm_Reg    : in boolean;

    -- OpSel1_FSR : in boolean;
    FSR : in std_logic_vector(0 to 4);

    Reg1  : out std_logic_vector(0 to C_DATA_SIZE-1) := (others => '0');
    Op1   : out std_logic_vector(0 to C_DATA_SIZE-1) := (others => '0');
    Op2   : out std_logic_vector(0 to C_DATA_SIZE-1) := (others => '0');
    Op2_C : out std_logic_vector(0 to C_DATA_SIZE-1) := (others => '0');

    MFS_Reg_Sel             : in  std_logic_vector(0 to 2);
    BTR                     : in  BTR_TYPE;
    EAR                     : in  EAR_TYPE;
    EDR                     : in  EDR_TYPE;
    ESR                     : in  ESR_TYPE;
    word_r1_r2_unalignment  : out std_logic;
    word_r1_imm_unalignment : out std_logic;
    halfword_unalignment    : out std_logic
    );

end entity Operand_Select;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of Operand_Select is

  component Operand_Select_Bit is
    generic (
      C_TARGET             : TARGET_FAMILY_TYPE;
      C_EXCEPTION_ADDR_BIT : std_logic := '0';
      C_INTERRUPT_ADDR_BIT : std_logic := '0';
      C_EXT_BRK_ADDR_BIT   : std_logic := '0';
      C_ONLY_PC            : boolean   := false;
      C_DEBUG_ENABLED      : integer   := 0;
      C_LOWER_HALFWORD     : boolean   := true;
      C_LSB_BIT            : boolean   := true
      );
    port (
      Clk              : in  std_logic;
      Reset            : in  boolean;
      OF_PipeRun       : in  boolean;
      Reg1_Data        : in  std_logic;
      EX_Result        : in  std_logic;
      Res_Forward1     : in  boolean;
      MSR              : in  std_logic;
      PC_OF            : in  std_logic;
      Enable_MSR       : in  std_logic;
      OpSel1_PC        : in  boolean;
      OpSel1_SPR       : in  boolean;
      Reg2_Data        : in  std_logic;
      Res_Forward2     : in  boolean;
      Sign_Imm         : in  std_logic;
      Imm_Reg          : in  std_logic;
      Use_Imm_Reg      : in  boolean;
      OpSel2_Imm       : in  boolean;
      Take_Exception   : in  boolean;
      Take_Interrupt   : in  boolean;
      Take_Ext_BRK     : in  boolean;
      Exception_or_BRK : in  boolean;
      Store_PC_For_Intr      : in boolean;
      Store_PC_For_Intr_NoImm: in boolean;
      Reg1             : out std_logic;
      Op1              : out std_logic;
      Op2              : out std_logic;
      Op2_C            : out std_logic);
  end component Operand_Select_Bit;

  constant INTR_ADDR : std_logic_vector(0 to C_DATA_SIZE-1) :=
    std_logic_vector(to_signed(String_To_Int(C_INTERRUPT_ADDR), C_DATA_SIZE));

  constant EXC_ADDR : std_logic_vector(0 to C_DATA_SIZE-1) :=
    std_logic_vector(to_signed(String_To_Int(C_EXCEPTION_ADDR), C_DATA_SIZE));

  constant EXT_BRK_ADDR : std_logic_vector(0 to C_DATA_SIZE-1) :=
    std_logic_vector(to_signed(String_To_Int(C_EXT_BRK_ADDR), C_DATA_SIZE));

  signal sign_Imm       : std_logic_vector(0 to C_DATA_SIZE-1);
  signal imm_Extend_Reg : std_logic_vector(0 to C_DATA_SIZE-1);

  signal spr_zero_extended : std_logic_vector(0 to C_DATA_SIZE-1);
  signal Enable_SPR_I      : std_logic_vector(0 to C_DATA_SIZE-1);
  signal exception_or_brk  : boolean;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin

  -----------------------------------------------------------------------------
  -- Operand 1 Mux and DFF
  -- Oper1 =
  -- MSR      when OpSel1_MSR and not(OpSel1_PC) and OpSel1_SPR
  -- Link_Reg when not(OpSel1_MSR) and not(OpSel1_PC) and OpSel1_SPR
  -- PC       when OpSel1_PC and OpSel1_SPR
  -- Reg      when not(OpSel1_SPR)
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Operand 2 Mux and DFF
  -- Oper2 =
  -- Imm_Reg & Imm_Value  when Use_Imm_Reg and OpSel2_Imm
  -- Sign_Ext(Imm_Value)  when not(Use_Imm_Reg) and OpSel2_Imm
  -- Reg                  when not(OpSel2_Imm)
  -----------------------------------------------------------------------------

  Sign_Zero_Extend_Imm_Value : process (Imm_Value) is
  begin  -- process Sign_Zero_Extend_Imm_Value
    if (C_DATA_SIZE < 16) then
      sign_Imm <= Imm_Value(16-C_DATA_SIZE to 15);
    else
      sign_Imm                                  <= (others => Imm_Value(0));
      sign_Imm(C_DATA_SIZE-16 to C_DATA_SIZE-1) <= Imm_Value(0 to 15);
    end if;
  end process Sign_Zero_Extend_Imm_Value;

  Using_FPGA : if (C_TARGET /= RTL) generate
    -- Operand_Select_Bit does not include logic for muxing in SPR for these
    -- bits if there are no exceptions or PVR. If exceptions and/or PVR are
    -- enabled the corresponding bits are also muxed.
    constant OpSelect_Bits_Only_PC : Boolean_array(0 to 31) := (
      0        => false,
      1  to 20 => (not C_USE_EXCEPTIONS),
      21       => (not C_USE_EXCEPTIONS) and (C_PVR = 0),
      22 to 23 => (not C_USE_EXCEPTIONS),
      24 to 31 => false);
  begin
    -- Necessary for correct high halfword exception address on BRK
    exception_or_brk <= Take_Ext_BRK or Take_Exception;

    OpSelect_Bits : for I in C_DATA_SIZE-1 downto 0 generate
    begin
      Operand_Select_Bit_I : Operand_Select_Bit
        generic map (
          C_TARGET             => C_TARGET,
          C_EXCEPTION_ADDR_BIT => EXC_ADDR(I),
          C_INTERRUPT_ADDR_BIT => INTR_ADDR(I),
          C_EXT_BRK_ADDR_BIT   => EXT_BRK_ADDR(I),
          C_ONLY_PC            => OpSelect_Bits_Only_PC(I),
          C_DEBUG_ENABLED      => C_DEBUG_ENABLED,
          C_LOWER_HALFWORD     => (I > 15),
          C_LSB_BIT            => (I >C_DATA_SIZE-3)
          )
        port map (
          Clk              => Clk,                   -- [in]
          Reset            => Reset,                 -- [in]
          OF_PipeRun       => OF_PipeRun,            -- [in]
          Reg1_Data        => Reg1_Data(I),          -- [in]
          EX_Result        => EX_Result(I),          -- [in]
          Res_Forward1     => Res_Forward1,          -- [in]
          MSR              => spr_zero_extended(I),  -- [in]
          Enable_MSR       => Enable_SPR_I(I),       -- [in]
          PC_OF            => PC_OF(I),              -- [in]
          OpSel1_PC        => OpSel1_PC,             -- [in]
          OpSel1_SPR       => OpSel1_SPR,            -- [in]
          Reg2_Data        => Reg2_Data(I),          -- [in]
          Res_Forward2     => Res_Forward2,          -- [in]
          Sign_Imm         => Sign_Imm(I),           -- [in]
          Imm_Reg          => imm_Extend_Reg(I),     -- [in]
          Use_Imm_Reg      => Use_Imm_Reg,           -- [in]
          OpSel2_Imm       => OpSel2_Imm,            -- [in]
          Take_Exception   => Take_Exception,        -- [in]
          Take_Interrupt   => Take_Interrupt,        -- [in]
          Take_Ext_BRK     => Take_Ext_BRK,          -- [in]
          Exception_or_BRK => exception_or_brk,      -- [in]
          Store_PC_For_Intr      =>Store_PC_For_Intr,       -- [in]
          Store_PC_For_Intr_NoImm=>Store_PC_For_Intr_NoImm, -- [in]
          Reg1             => Reg1(I),               -- [out]
          Op1              => Op1(I),                -- [out]
          Op2              => Op2(I),                -- [out]
          Op2_C            => Op2_C(I));             -- [out]
    end generate OpSelect_Bits;
  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate
    signal Op1_I   : std_logic_vector(0 to C_DATA_SIZE-1);
    signal Reg1_I  : std_logic_vector(0 to C_DATA_SIZE-1);
    signal Op2_I   : std_logic_vector(0 to C_DATA_SIZE-1);
    signal Op2_C_I : std_logic_vector(0 to C_DATA_SIZE-1);
  begin

    Op1_Handle : process (Res_Forward1, EX_Result, Reg1_Data,
                          OpSel1_PC, PC_OF, spr_zero_extended, OpSel1_SPR) is
      variable reg1 : std_logic_vector(0 to C_DATA_SIZE-1);
      variable imm1 : std_logic_vector(0 to C_DATA_SIZE-1);
    begin  -- process Op1_Handle
      if (Res_Forward1) then
        reg1 := EX_Result;
      else
        reg1 := Reg1_Data;
      end if;
      if (OpSel1_PC) then
        imm1 := PC_OF;
      else
        imm1 := spr_zero_extended;
      end if;
      if (OpSel1_SPR) then
        Op1_I <= imm1;
      else
        Op1_I <= reg1;
      end if;
      Reg1_I <= reg1;
    end process Op1_Handle;

    Op1_DFF : process (Clk) is
    begin  -- process Op1_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        for I in 0 to C_DATA_SIZE-1 loop
          if (OF_PipeRun) then
            Reg1(I) <= Reg1_I(I);
            Op1(I)  <= Op1_I(I);
          end if;
        end loop;  -- I
      end if;
    end process Op1_DFF;

    Op2_Handle : process (EX_Result, OpSel2_Imm, Reg2_Data, Res_Forward2,
                          Sign_Imm, Take_Ext_BRK, Take_Interrupt, Take_Exception,
                          Use_Imm_Reg, imm_Extend_Reg) is
      variable reg2 : std_logic_vector(0 to C_DATA_SIZE-1);
      variable imm2 : std_logic_vector(0 to C_DATA_SIZE-1);
    begin  -- process Op2_Handle
      if (Take_Interrupt) then
        reg2 := INTR_ADDR;