shift_logic.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      signal res_10     : std_logic;
      signal res_11     : std_logic;
      signal res_1x     : std_logic;
      signal byte1_0x   : std_logic;
      signal byte2_0x   : std_logic;
      signal byte3_0x   : std_logic;
      signal byte4_0x   : std_logic;
      signal normal_res : std_logic_vector(0 to 2);
    begin
      -- Generate control signals for the different pcmp instructions.
      Is_PCMP    <= '1' when PCMP_Instr                                                              else '0';
      Is_PCMP_0x <= '1' when PCMP_Instr and Logic_Oper(PCMP_LOGIC_DEC_BIT) = PCMP_LOGIC_DEC_BYTEOPS  else '0';
      Is_PCMP_1x <= '1' when PCMP_Instr and Logic_Oper(PCMP_LOGIC_DEC_BIT) /= PCMP_LOGIC_DEC_BYTEOPS else '0';
      
      -- Check if bytes are equal.
      carry_equal_byte1 : carry_equal
        generic map (
          C_TARGET => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          Size     => 8)                -- [natural]
        port map (
          A_Vec      => Op1(0 to 7),    -- [in  std_logic_vector(0 to Size-1)]
          B_Vec      => Op2(0 to 7),    -- [in  std_logic_vector(0 to Size-1)]
          Enable     => Is_PCMP,        -- [in std_logic]
          Is_Equal_1 => byte1,          -- [out std_logic]
          Enable_2   => Is_PCMP_0x,     -- [in std_logic]
          Is_Equal_2 => byte1_0x);      -- [out std_logic]

      carry_equal_byte2 : carry_equal
        generic map (
          C_TARGET => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          Size     => 8)                -- [natural]
        port map (
          A_Vec      => Op1(8 to 15),   -- [in  std_logic_vector(0 to Size-1)]
          B_Vec      => Op2(8 to 15),   -- [in  std_logic_vector(0 to Size-1)]
          Enable     => Is_PCMP,        -- [in std_logic]
          Is_Equal_1 => byte2,          -- [out std_logic]
          Enable_2   => Is_PCMP_0x,     -- [in std_logic]
          Is_Equal_2 => byte2_0x);      -- [out std_logic]

      carry_equal_byte3 : carry_equal
        generic map (
          C_TARGET => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          Size     => 8)                -- [natural]
        port map (
          A_Vec      => Op1(16 to 23),  -- [in  std_logic_vector(0 to Size-1)]
          B_Vec      => Op2(16 to 23),  -- [in  std_logic_vector(0 to Size-1)]
          Enable     => Is_PCMP,        -- [in std_logic]
          Is_Equal_1 => byte3,          -- [out std_logic]
          Enable_2   => Is_PCMP_0x,     -- [in std_logic]
          Is_Equal_2 => byte3_0x);      -- [out std_logic]

      carry_equal_byte4 : carry_equal
        generic map (
          C_TARGET => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          Size     => 8)                -- [natural]
        port map (
          A_Vec      => Op1(24 to 31),  -- [in  std_logic_vector(0 to Size-1)]
          B_Vec      => Op2(24 to 31),  -- [in  std_logic_vector(0 to Size-1)]
          Enable     => Is_PCMP,        -- [in std_logic]
          Is_Equal_1 => byte4,          -- [out std_logic]
          Enable_2   => Is_PCMP_0x,     -- [in std_logic]
          Is_Equal_2 => byte4_0x);      -- [out std_logic]

      -- Instr_OF(4 to 5) = "0x" (pcmpbf)
      pcmp_00_lut_0 : LUT4
        generic map(
          INIT => X"0002"
          )
        port map (
          O  => res_00(0),              -- [out]
          I0 => byte4_0x,               -- [in]
          I1 => byte3_0x,               -- [in]
          I2 => byte2_0x,               -- [in]
          I3 => byte1_0x);              -- [in]

      pcmp_00_lut_1 : LUT4
        generic map(
          INIT => X"00FC"
          )
        port map (
          O  => res_00(1),              -- [out]
          I0 => byte4_0x,               -- [in]
          I1 => byte3_0x,               -- [in]
          I2 => byte2_0x,               -- [in]
          I3 => byte1_0x);              -- [in]

      pcmp_00_lut_2 : LUT4
        generic map(
          INIT => X"FF0C"
          )
        port map (
          O  => res_00(2),              -- [out]
          I0 => byte4_0x,               -- [in]
          I1 => byte3_0x,               -- [in]
          I2 => byte2_0x,               -- [in]
          I3 => byte1_0x);              -- [in]      

      -- If Instr_OF(5) = "0" return 1 if match, 0 if not match (pcmpeq)
      pcmp_10_lut : LUT4
        generic map(
          INIT => X"8000"
          )
        port map (
          O  => res_10,                 -- [out]
          I0 => byte4,                  -- [in]
          I1 => byte3,                  -- [in]
          I2 => byte2,                  -- [in]
          I3 => byte1);                 -- [in]      

      -- If Instr_OF(5) = "1" return 0 if match, 1 if not match (pcmpne)
      pcmp_11_lut : LUT4
        generic map(
          INIT => X"7FFF"
          )
        port map (
          O  => res_11,                 -- [out]
          I0 => byte4,                  -- [in]
          I1 => byte3,                  -- [in]
          I2 => byte2,                  -- [in]
          I3 => byte1);                 -- [in]      
      
      -- Select from eq or ne.
      MUXF5_pcmp1x : MUXF5
        port map (
          O  => res_1x,                            -- [out std_logic]
          I0 => res_10,                            -- [in  std_logic]
          I1 => res_11,                            -- [in  std_logic]
          S  => Logic_Oper(PCMP_LOGIC_DEC2_BIT));  -- [in std_logic]

      -- Generate final result for all supported instructions.
      -- (Clear "top" bits for pcmp instruction)
      Shift_Logic_Result_i(24) <= (not Is_PCMP) and Shift_Logic_Result_ii(24);
      Shift_Logic_Result_i(25) <= (not Is_PCMP) and Shift_Logic_Result_ii(25);
      Shift_Logic_Result_i(26) <= (not Is_PCMP) and Shift_Logic_Result_ii(26);
      Shift_Logic_Result_i(27) <= (not Is_PCMP) and Shift_Logic_Result_ii(27);
      Shift_Logic_Result_i(28) <= (not Is_PCMP) and Shift_Logic_Result_ii(28);

      -- Clear result from shift/logic for pcmp instructions.
      normal_res(0) <= (not Is_PCMP) and Shift_Logic_Result_ii(29);
      normal_res(1) <= (not Is_PCMP) and Shift_Logic_Result_ii(30);
      normal_res(2) <= (not Is_PCMP) and Shift_Logic_Result_ii(31);
      
      -- Mux the least significant bits between shift/logic and pcmp.
      shift_logic_result_i_lut_0 : LUT2
        generic map(INIT => X"E")
        port map (
          O  => Shift_Logic_Result_i(29),  -- [out]
          I0 => normal_res(0),             -- [in]
          I1 => res_00(0));                -- [in]      

      shift_logic_result_i_lut_1 : LUT2
        generic map(INIT => X"E" )
        port map (
          O  => Shift_Logic_Result_i(30),  -- [out]
          I0 => normal_res(1),             -- [in]
          I1 => res_00(1));                -- [in]      

      shift_logic_result_i_lut_2 : LUT4
        generic map(
          INIT => X"F0EE"
          )
        port map (
          O  => Shift_Logic_Result_i(31),  -- [out]
          I0 => normal_res(2),             -- [in]
          I1 => res_00(2),                 -- [in]
          I2 => res_1x,                    -- [in]
          I3 => Is_PCMP_1x);               -- [in]      

    end generate Using_FPGA;

    Using_RTL: if (C_TARGET = RTL) generate
      byte1 <= '1' when Op1(0 to 7) = Op2(0 to 7)     else '0';
      byte2 <= '1' when Op1(8 to 15) = Op2(8 to 15)   else '0';
      byte3 <= '1' when Op1(16 to 23) = Op2(16 to 23) else '0';
      byte4 <= '1' when Op1(24 to 31) = Op2(24 to 31) else '0';

      The_Logic : process (Logic_Oper, byte1, byte2, byte3, byte4, PCMP_Instr,
                           Shift_Logic_Result_ii) is
        variable res_i  : std_logic_vector(29 to 31);
        variable normal : std_logic;
      begin  -- process The_Logic    
        if Logic_Oper(PCMP_LOGIC_DEC_BIT) = PCMP_LOGIC_DEC_BYTEOPS then  -- Instr_OF(4)
          -- Instr_OF(4 to 5) = "00" (pcmpbf)
          -- Removed instruction: Instr_OF(4 to 5) = "01" (pcmpbc) Count equal from left.
          -- => (pcmpbf) decoded as "0x"
          -- Find index of first byte match
          if (byte1 = '1') then
            res_i := "001";
          elsif (byte2 = '1') then
            res_i := "010";
          elsif (byte3 = '1') then
            res_i := "011";
          elsif (byte4 = '1') then
            res_i := "100";
          else
            res_i := "000";
          end if;
        else
          -- Instr_OF(4) = "1"
          -- Compare if the two registers match
          -- If Instr_OF(5) = "0" return 1 if match, 0 if not match (pcmpeq)
          -- If Instr_OF(5) = "1" return 0 if match, 1 if not match (pcmpne)
          res_i(29 to 30) := "00";
          if (byte1 = '1' and byte2 = '1' and byte3 = '1' and byte4 = '1') then
            res_i(31) := not Logic_Oper(PCMP_LOGIC_DEC2_BIT);
          else
            res_i(31) := Logic_Oper(PCMP_LOGIC_DEC2_BIT);
          end if;
        end if;

        -- Normal result or pcmp result
        if PCMP_Instr then
          normal := '0';
        else
          normal := '1';
        end if;

        -- pcmp result if not normal
        Shift_Logic_Result_i(24) <= Normal and Shift_Logic_Result_ii(24);
        Shift_Logic_Result_i(25) <= Normal and Shift_Logic_Result_ii(25);
        Shift_Logic_Result_i(26) <= Normal and Shift_Logic_Result_ii(26);
        Shift_Logic_Result_i(27) <= Normal and Shift_Logic_Result_ii(27);
        Shift_Logic_Result_i(28) <= Normal and Shift_Logic_Result_ii(28);
        Shift_Logic_Result_i(29) <= (Normal and Shift_Logic_Result_ii(29)) or (not Normal and res_i(29));
        Shift_Logic_Result_i(30) <= (Normal and Shift_Logic_Result_ii(30)) or (not Normal and res_i(30));
        Shift_Logic_Result_i(31) <= (Normal and Shift_Logic_Result_ii(31)) or (not Normal and res_i(31));
      end process The_Logic;

    end generate Using_RTL;

    Shift_Logic_Result_i(0 to 23) <= Shift_Logic_Result_ii(0 to 23);
  end generate Use_PCMP_instr;

  -----------------------------------------------------------------------------
  -- Carry out is always the LSB of Op1
  -----------------------------------------------------------------------------
  Shift_Carry_Out <= Op1(Op1'right);
  
end architecture IMP;