shift_logic.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: shift_logic.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Shift_Logic - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        shift_logic.vhd
-- Version:         v1.00a
-- Description:     Implement the functions needed for shift right and the
--                  logical instructions
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              shift_logic.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version of entity
--   goran  2001-03-09    First Version of architecture
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Shift_Logic_Module is
  generic (
    C_USE_PCMP_INSTR : boolean               := true;
    C_DATA_SIZE      : natural range 1 to 64 := 32;
    C_TARGET         : TARGET_FAMILY_TYPE
    );
  port (
    Op1                : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Op2                : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Shift_Carry_In     : in  std_logic;
    Sext8              : in  boolean;
    Sext16             : in  boolean;
    -- Sext32             : in  boolean;
    Sign_Extend        : in  boolean;
    Shift_Oper         : in  std_logic_vector(0 to 1);
    Logic_Oper         : in  std_logic_vector(0 to 1);
    PCMP_Instr         : in  boolean;
    Select_Logic       : in  boolean;
    -- Logic_Result       : out std_logic_vector(0 to C_DATA_SIZE-1);
    Shift_Logic_Result : out std_logic_vector(0 to C_DATA_SIZE-1);
    Shift_Carry_Out    : out std_logic
    );

end entity Shift_Logic_Module;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;

architecture IMP of Shift_Logic_Module is

  component Shift_Logic_Bit is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Op1             : in  std_logic;
      Op2             : in  std_logic;
      Shifted         : in  std_logic;
      Sext            : in  std_logic;
      Logic_Oper      : in  std_logic_vector(0 to 1);
      Shift_Oper      : in  std_logic;
      Select_Logic    : in  boolean;
      -- Logic_Res       : out std_logic;
      Shift_Logic_Res : out std_logic);
  end component Shift_Logic_Bit;

  component carry_equal is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      Size     : natural);
    port (
      A_Vec      : in  std_logic_vector(0 to Size-1);
      B_Vec      : in  std_logic_vector(0 to Size-1);
      Enable     : in  std_logic;
      Is_Equal_1 : out std_logic;
      Enable_2   : in  std_logic;
      Is_Equal_2 : out std_logic);
  end component carry_equal;

  signal right_Shifted : std_logic_vector(Op1'range);  -- Right shift
  signal sext          : std_logic_vector(Op1'range);  -- Sign extend
  signal msb           : std_logic;

  -- signal or_Oper          : std_logic;
  signal sign_extend_oper : std_logic;  -- std_logic version of boolean

  -- signals for muxing the shift_logic
  signal Shift_Logic_Result_i  : std_logic_vector(0 to C_DATA_SIZE-1);
  signal Shift_Logic_Result_ii : std_logic_vector(0 to C_DATA_SIZE-1);

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
  
begin

  sign_extend_oper <= '1' when Sign_Extend else '0';

  -----------------------------------------------------------------------------
  -- Calculate the new MSB bit for all shift operation
  -----------------------------------------------------------------------------
  Shift_Operation : process (Shift_Oper, Op1, Shift_Carry_In) is
  begin  -- process Shift_Operation
    case Shift_Oper is
      when "00"   => msb <= Op1(Op1'left);   -- SRA
      when "01"   => msb <= Shift_Carry_In;  -- SRC
      when "10"   => msb <= '0';             -- SRL
      when others => msb <= '0';
    end case;
  end process Shift_Operation;

  -- Do the right shift
  right_Shifted <= MSB & Op1(0 to C_DATA_SIZE-2);

  -- Generate the Sign Extended bus (Sext)
  Sign_Extend_Handler : process (Op1, Sext8, Sext16) is
    variable byte_sign     : std_logic_vector(0 to C_DATA_SIZE-9);
    variable halfword_sign : std_logic_vector(0 to C_DATA_SIZE-1);
  begin  -- process Sign_Extend_Handler
    Sext <= (others => '0');            -- Always Pass
    if (C_DATA_SIZE > 8) then
      if Sext8 then
        byte_sign                := (others => Op1(C_DATA_SIZE-8));
        Sext(0 to C_DATA_SIZE-9) <= byte_sign;
      end if;
      if (C_DATA_SIZE > 16) then
        if Sext16 then
          halfword_sign                         := (others => Op1(C_DATA_SIZE-16));
          Sext(C_DATA_SIZE-16 to C_DATA_SIZE-9) <= "00000000";
          Sext(0 to C_DATA_SIZE-17)             <= halfword_sign(0 to C_DATA_SIZE-17);
        end if;
      end if;
    end if;
  end process Sign_Extend_Handler;


  Using_FPGA : if (C_TARGET /= RTL) generate
    Shift_Logic_Bits : for I in C_DATA_SIZE-1 downto 0 generate
      Shift_Logic_Bit_I : Shift_Logic_Bit
        generic map (
          C_TARGET => C_TARGET)
        port map (
          Op1             => Op1(I),                     -- [in]
          Op2             => Op2(I),                     -- [in]
          Shifted         => right_Shifted(I),           -- [in]
          Sext            => Sext(I),                    -- [in]
          Logic_Oper      => Logic_Oper,                 -- [in]
          Shift_Oper      => sign_extend_oper,           -- [in]
          Select_Logic    => Select_Logic,               -- [in]
          -- Logic_Res       => Logic_Result(I),            -- [out]
          Shift_Logic_Res => Shift_Logic_Result_ii(I));  -- [out]

    end generate Shift_Logic_Bits;
  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate

    SHIFT_LOGIC_PROCESS : process (Op1, Op2, right_Shifted, Sext, Logic_Oper, sign_extend_oper, Select_Logic) is
      variable Logic_res : std_logic_vector(Op1'range);
    begin  -- process Shift_Logic_Process
      case Logic_Oper is
        when "00"   => Logic_res := Op1 or Op2;
        when "01"   => Logic_res := Op1 and Op2;
        when "10"   => Logic_res := Op1 xor Op2;
        when "11"   => Logic_res := Op1 and not Op2;
        when others => null;
      end case;
      if (Select_Logic) then
        Shift_Logic_Result_ii <= Logic_res;
      else
        if (sign_extend_oper = '1') then
          Shift_Logic_Result_ii <= Op1 or Sext;
        else
          Shift_Logic_Result_ii <= right_Shifted;
        end if;
      end if;
    end process SHIFT_LOGIC_PROCESS;
  end generate Using_RTL;

  Shift_Logic_Result <= Shift_Logic_Result_i;

  -----------------------------------------------------------------------------
  -- Extra Instructions (PCMP)
  -----------------------------------------------------------------------------
  No_PCMP_instr : if (not C_USE_PCMP_INSTR) generate
    Shift_Logic_Result_i <= Shift_Logic_Result_ii;
  end generate No_PCMP_instr;

  Use_PCMP_instr : if (C_USE_PCMP_INSTR) generate
    signal byte1 : std_logic;
    signal byte2 : std_logic;
    signal byte3 : std_logic;
    signal byte4 : std_logic;
  begin

    -- Check if the bytes in the two registers match
    Using_FPGA: if (C_TARGET /= RTL) generate
      signal Is_PCMP    : std_logic;
      signal Is_PCMP_0x : std_logic;
      signal Is_PCMP_1x : std_logic;
      signal res_00     : std_logic_vector(0 to 2);