data_read_steering.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: data_read_steering.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Data_Read_Steering - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        data_read_steering.vhd
-- Version:         v1.00a
-- Description:     Read Steering logic     
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              data_read_steering.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-05-23    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- library and use statements
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;


-----------------------------------------------------------------------------
-- Port declarations
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--          C_TARGET        -- Xilinx target family, legal values are
--                             VIRTEX and VIRTEX2 (not a string)
--          C_U_SET         -- which USER SET the RLOC parameters belong to
--          C_DW            -- width of data buses
--          C_NB            -- number of data buses
--          C_BE            -- TRUE=Big Endian, FALSE=Little Endian
-- Definition of Ports:
--          D               -- data input (Dbus0, Dbus1, Dbus2, ...)
--          S               -- select input (S0,S1,S2,...) S0 most significant
--          Y               -- mux output Y = Dbus(S)
--          YL              -- mux output before last mux stage 
-------------------------------------------------------------------------------

entity Data_Read_Steering is

  generic (
    C_TARGET : TARGET_FAMILY_TYPE
    );
  port (
    D_In    : in  std_logic_vector(0 to 31);
    Sel_LSB : in  std_logic_vector(0 to 1);
    D_Out   : out std_logic_vector(0 to 31)
    );

end entity Data_Read_Steering;

-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------

library Unisim;
use Unisim.vcomponents.all;

architecture IMP of Data_Read_Steering is

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- architecture IMP

  D_Out(0 to 15) <= D_In(0 to 15);

  GEN_LOOP : for i in 0 to 7 generate
    signal lut_in0     : std_logic_vector(0 to 2);
    signal lut_in1     : std_logic_vector(0 to 2);
    signal mux_f5_in   : std_logic_vector(0 to 1);
    signal mux_f5_sel  : std_logic;
    signal mux_f5_inI0 : std_logic;
    signal mux_f5_inI1 : std_logic;
  begin
    lut_in0(2)      <= Sel_LSB(0);
    lut_in1(2)      <= Sel_LSB(0);
    mux_f5_sel      <= Sel_LSB(1);
    mux_f5_inI0     <= mux_f5_in(0);
    mux_f5_inI1     <= mux_f5_in(1);
    lut_in0(0 to 1) <= (D_In(7-i), D_In(23-i));
    lut_in1(0 to 1) <= (D_In(15-i), D_In(31-i));
    D_Out(23-i)     <= mux_f5_in(0);

    LUT30_I : LUT3
      generic map(
        INIT => X"CA"
        )
      port map (
        O  => mux_f5_in(0),             -- [out]
        I0 => lut_in0(0),               -- [in]
        I1 => lut_in0(1),               -- [in]
        I2 => lut_in0(2));              -- [in]
    LUT31_I : LUT3
      generic map(
        INIT => X"CA"
        )
      port map (
        O  => mux_f5_in(1),             -- [out]
        I0 => lut_in1(0),               -- [in]
        I1 => lut_in1(1),               -- [in]
        I2 => lut_in1(2));              -- [in]
    MUXF5_I : MUXF5
      port map (
        O  => D_Out(31-i),              --[out]
        I0 => mux_f5_inI0,              --[in]
        I1 => mux_f5_inI1,              --[in]
        S  => mux_f5_sel                --[in]
        );
  end generate GEN_LOOP;
end architecture IMP;