all_zero_detect.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: all_zero_detect.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- all_zero_detect.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2004 by Xilinx, Inc. All rights reserved.               **
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--  **  standard level Xilinx Hotline support, and will only address         **
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--
-------------------------------------------------------------------------------
-- Filename:        all_zero_detect.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              all_zero_detect.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2004-09-28    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity all_zero_detect is 
  generic (
    Size : natural);
  port (
    In_Vec  : in  std_logic_vector(0 to Size-1);
    Is_Zero : out boolean);
end entity all_zero_detect;

library unisim;
use unisim.vcomponents.all;

architecture IMP of all_zero_detect is

  -- Split signal into quarters so that it can be broken into LUT4s
  signal sel   : std_logic_vector(0 to ((Size+3)/4) - 1);
  signal carry : std_logic_vector(0 to ((Size+3)/4) );

  signal sig1 : std_logic_vector(0 to sel'length*4 - 1);
  
begin  -- architecture IMP

  -- If sig1 is not evenly divisable by 4, assign left over bits low
  -- so that the bits pass the all zero check.
  assign_sig1 : process (In_Vec) is
  begin  -- process assign_sig1
    sig1              <= (others => '0');
    sig1(0 to Size-1) <= In_Vec;
  end process assign_sig1;

  -- Set initial carry in the chain to 1
  carry(carry'right) <= '1';
  
  The_Compare: for I in sel'right downto sel'left generate

    -- inferred NOR4 (LUT4)
    sel(I) <= not (sig1(I*4) or sig1(I*4+1) or sig1(I*4+2) or sig1(I*4+3));

    -- Use carry chain to check iff all the NOR4s are one.
    -- The NOR4 output is the select bit, when 1 the chain passes the previous value down the chain
    -- If any NOR4 output is 0, the MUX uses the DI '0' and passes it down the rest of the chain
    -- The initial value in the chain is 1, so if all NOR4s are 1 then the 1 is passed down the entire chain
    MUXCY_L_I1 : MUXCY_L
      port map (
        DI => '0',                  -- [in  std_logic S = 0]
        CI => Carry(I+1),             -- [in  std_logic S = 1]
        S  => sel(I),             -- [in  std_logic (Select)]
        LO => Carry(I));              -- [out std_logic]    
  end generate The_Compare;

  Is_Zero <= Carry(0) = '1';
  
end architecture IMP;