prefetch_buffer.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: prefetch_buffer.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- PreFetch_Buffer - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        prefetch_buffer.vhd
-- Version:         v1.00a
-- Description:     Implement the Instruction prefetch buffer
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              prefetch_buffer.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library Unisim;
use Unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity PreFetch_Buffer is
  generic (
    C_TARGET             : TARGET_FAMILY_TYPE;
    C_FSL_ATOMIC         : integer;
    C_IEXT_BUS_EXCEPTION : integer
    ); 
  port (
    Clk         : in  std_logic;
    Reset       : in  boolean;
    IReady      : in  std_logic;
    OF_PipeRun  : in  std_logic;
    Jump        : in  boolean;
    Instr_Data  : in  std_logic_vector(0 to 31+C_IEXT_BUS_EXCEPTION+C_FSL_ATOMIC);
    Valid_Fetch : out std_logic;
    OF_Valid    : out boolean;
    Buffer_Full : out boolean;
    Instr_OF    : out std_logic_vector(0 to 31+C_IEXT_BUS_EXCEPTION+C_FSL_ATOMIC);
    Buffer_Addr : out std_logic_vector(0 to 3)
    );

end entity PreFetch_Buffer;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of PreFetch_Buffer is

  signal buffer_Addr_Sum   : std_logic_vector(1 to 3);
  signal buffer_Addr_Carry : std_logic_vector(1 to 4);
  signal reset_Buffer_Addr : std_logic;

  signal of_Valid_early : std_logic;
  signal of_Valid_I     : std_logic;
  signal buffer_Full_I  : std_logic;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
  
begin  -- architecture IMP

  Valid_Fetch <= IReady;

  -- Share the booleans so that we do not need to make these resolved booleans
  OF_Valid    <= (of_Valid_I = '1');
  Buffer_Full <= (buffer_Full_I = '1');
  
  Using_FPGA : if (C_TARGET /= RTL) generate
    signal buffer_Addr_I     : std_logic_vector(1 to 3);
    signal buffer_Addr_S_I   : std_logic_vector(1 to 3);
  begin
    
    PreFetch_Buffers : for I in 0 to 31+C_IEXT_BUS_EXCEPTION+C_FSL_ATOMIC generate
      SRL16E_I : SRL16E
        port map (
          CE  => IReady,                -- [in]
          D   => Instr_Data(I),         -- [in]
          Clk => Clk,                   -- [in]
          A0  => buffer_Addr_I(3),      -- [in]
          A1  => buffer_Addr_I(2),      -- [in]
          A2  => buffer_Addr_I(1),      -- [in]
          A3  => '0',      -- [in]
          Q   => Instr_OF(I));          -- [out]

    end generate PreFetch_Buffers;

    buffer_Full_I <= (buffer_Addr_I(1)) and  -- (buffer > 3) 
                     of_Valid_I;        --  but not Empty

    reset_Buffer_Addr <= '1' when Jump or Reset else '0';

    buffer_Addr_Carry(4) <= IReady;

    Buffer_DFFs : for I in 1 to 3 generate
      buffer_Addr_Sum(I) <= buffer_Addr_I(I) xor of_PipeRun;
      
      buffer_Addr_MUXCY_L : MUXCY_L
        port map (
          DI => of_PipeRun,              -- [in  std_logic]
          CI => buffer_Addr_carry(I+1),  -- [in  std_logic]
          S  => buffer_Addr_Sum(I),      -- [in  std_logic]
          LO => buffer_Addr_carry(I));   -- [out std_logic]
      
      buffer_Addr_XORCY_I : XORCY
        port map (
          LI => buffer_Addr_Sum(I),      -- [in  std_logic]
          CI => buffer_Addr_carry(I+1),  -- [in  std_logic]
          O  => buffer_Addr_S_I(I));     -- [out std_logic]

      FDS_I : FDS
        port map (
          Q => buffer_Addr_I(I),        -- [out std_logic]
          D => buffer_Addr_S_I(I),      -- [in  std_logic]
          C => Clk,                     -- [in  std_logic]
          S => Reset_Buffer_Addr);      -- [in std_logic]
    end generate Buffer_DFFs;

    Buffer_Addr <= '0' & buffer_Addr_I(1 to 3);


--  of_Valid_I <= not(buffer_Addr_I(0) and buffer_Addr_I(1) and buffer_Addr_I(2) and buffer_Addr_I(3));


    of_valid_early <= not(buffer_Addr_S_I(1) and
                          buffer_Addr_S_I(2) and buffer_Addr_S_I(3));


    of_valid_FDR_I : FDR
      port map (
        Q => of_valid_I,                -- [out std_logic]
        D => of_valid_early,            -- [in  std_logic]
        C => Clk,                       -- [in  std_logic]
        R => Reset_Buffer_Addr);        -- [in std_logic]
    
  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate
    type SRL16_TYPE is array(0 to 15) of std_logic_vector(0 to 31+C_IEXT_BUS_EXCEPTION+C_FSL_ATOMIC);
    signal PC_Buffer : SRL16_TYPE;
    signal buffer_Addr_I     : std_logic_vector(0 to 3);
    signal buffer_Addr_S_I   : std_logic_vector(0 to 3);
    signal buffer_Addr_Incr  : std_logic_vector(0 to 3);
  begin

    PreFetch_Buffer : process (Clk) is
    begin  -- process PreFetch_Buffer
      if Clk'event and Clk = '1' then   -- rising clock edge
        if (IReady = '1') then
          for I in 15 downto 1 loop
            PC_Buffer(I) <= PC_Buffer(I-1);
          end loop;  -- I
          PC_Buffer(0) <= Instr_Data;
        end if;
      end if;
    end process PreFetch_Buffer;

    Instr_OF <= PC_Buffer(to_integer(unsigned(buffer_Addr_I)));

    buffer_Full_I <= (buffer_Addr_I(0) or buffer_Addr_I(1)) and  -- (buffer > 3) 
                     of_Valid_I;        --  but not Empty

    Buffer_Addr_Counter : process (IReady, OF_PipeRun) is
    begin  -- process Buffer_Addr_Counter
      if (IReady = '1') and (OF_PipeRun = '0') then     -- Loading and not moving the
                                            -- pipeline (PipeStall)
        buffer_Addr_Incr <= "0001";
      elsif (IReady = '0') and (OF_PipeRun = '1') then  -- Not loading but moving the
                                            -- pipeline (Using 1 instruction)
        buffer_Addr_Incr <= "1111";
      else
        buffer_Addr_Incr <= "0000";
      end if;
    end process Buffer_Addr_Counter;

    reset_Buffer_Addr <= '1' when Jump or Reset else '0';


    buffer_Addr_S_I <= std_logic_vector(unsigned(buffer_Addr_I) + unsigned(buffer_Addr_Incr));

    Buffer_Addr_DFF: process (Clk) is
    begin  -- process Buffer_Addr_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if reset_Buffer_Addr = '1' then             -- synchronous reset (active high)
          Buffer_Addr_I <= (others => '1');
        else
          Buffer_Addr_I <= buffer_Addr_S_I;
        end if;
      end if;
    end process Buffer_Addr_DFF;

    Buffer_Addr <= buffer_Addr_I;

    of_valid_early <= not(buffer_Addr_S_I(0) and buffer_Addr_S_I(1) and
                          buffer_Addr_S_I(2) and buffer_Addr_S_I(3));

    of_Valid_DFF: process (Clk) is
    begin  -- process of_Valid_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if reset_Buffer_Addr = '1' then             -- synchronous reset (active high)
          of_Valid_I <= '0';
        else
          of_Valid_I <= of_valid_early;
        end if;
      end if;
    end process of_Valid_DFF;

  end generate Using_RTL;

end architecture IMP;