mux4_8.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: mux4_8.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- mux_encode_sel - entity/architecture pair
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        mux_encode_sel_imp.vhd
-- Version:         v1.00a
-- Description:     Parameterizeable mux with binary encoded select
--                  
-------------------------------------------------------------------------------
-- Structure:   
--                  mux_encode_sel.vhd
--
-------------------------------------------------------------------------------
-- Author:          B.L. Tise
-- History:
--   BLT            2001-04-06    First Version
--   BLT            2001-05-08    Added 8:1 mux
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- library and use statements
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.vcomponents.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--          C_TARGET        -- Xilinx target family, legal values are
--                             VIRTEX and VIRTEXII (not a string)
--          C_Y             -- Y offset from origin of RPM (family-independent
--                             coordinate system)       Y
--          C_X             -- X offset from origin     ^
--                                                      |
--                                                      |
--                                                       ----> X
--          C_U_SET         -- which USER SET the RLOC parameters belong to
--          C_DW            -- width of data buses
--          C_NB            -- number of data buses
--          C_BE            -- TRUE=Big Endian, FALSE=Little Endian
-- Definition of Ports:
--          D               -- data input (Dbus0, Dbus1, Dbus2, ...)
--          S               -- select input (S0,S1,S2,...) S0 most significant
--          Y               -- mux output Y = Dbus(S)
--          YL              -- mux output before last mux stage 
-------------------------------------------------------------------------------

entity mux4_8 is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE;
    C_BE     : boolean := true
    );
  port (
    D  : in  std_logic_vector(0 to 31);
    S  : in  std_logic_vector(0 to 1);
    Y  : out std_logic_vector(0 to 7);
    YL : out std_logic_vector(0 to 7)
    );

end entity mux4_8;

-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------

architecture IMP of mux4_8 is
  constant C_DW : integer := 8;
  constant C_NB : integer := 4;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- architecture imp

  GEN_4 : if C_NB = 4 generate
    GEN4_LOOP : for i in 0 to C_DW-1 generate
      signal lut_in0     : std_logic_vector(0 to 2);
      signal lut_in1     : std_logic_vector(0 to 2);
      signal mux_f5_in   : std_logic_vector(0 to 1);
      signal mux_f5_sel  : std_logic;
      signal mux_f5_inI0 : std_logic;
      signal mux_f5_inI1 : std_logic;
    begin
      lut_in0(2)  <= S(0);
      lut_in1(2)  <= S(0);
      mux_f5_sel  <= S(1);
      mux_f5_inI0 <= mux_f5_in(0);
      mux_f5_inI1 <= mux_f5_in(1);
      GEN_BIGENDIAN : if C_BE generate
        lut_in0(0 to 1) <= (D(i+0*C_DW), D(i+2*C_DW));
        lut_in1(0 to 1) <= (D(i+1*C_DW), D(i+3*C_DW));
        YL(i)           <= mux_f5_in(0);
      end generate GEN_BIGENDIAN;
      GEN_LITENDIAN : if not C_BE generate
        lut_in0(0 to 1) <= (D(i+3*C_DW), D(i+1*C_DW));
        lut_in1(0 to 1) <= (D(i+2*C_DW), D(i+0*C_DW));
        YL(i)           <= mux_f5_in(0);
      end generate GEN_LITENDIAN;
      LUT30_I : LUT3
        generic map(
          INIT => X"CA"
          )
        port map (
          O  => mux_f5_in(0),           -- [out]
          I0 => lut_in0(0),             -- [in]
          I1 => lut_in0(1),             -- [in]
          I2 => lut_in0(2));            -- [in]
      LUT31_I : LUT3
        generic map(
          INIT => X"CA"
          )
        port map (
          O  => mux_f5_in(1),           -- [out]
          I0 => lut_in1(0),             -- [in]
          I1 => lut_in1(1),             -- [in]
          I2 => lut_in1(2));            -- [in]
      MUXF5_I : MUXF5
        port map (
          O  => Y(i),                   --[out]
          I0 => mux_f5_inI0,            --[in]
          I1 => mux_f5_inI1,            --[in]
          S  => mux_f5_sel              --[in]
          );
    end generate GEN4_LOOP;
  end generate GEN_4;

end architecture IMP;