result_mux_bit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: result_mux_bit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Result_Mux_Bit - entity/architecture 
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        result_mux_bit.vhd
-- Version:         v1.00a
-- Description:     Implements 1 bit in the result mux
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              result_mux_bit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Result_Mux_Bit is

  generic (
    C_TARGET : TARGET_FAMILY_TYPE);
  port (
    Clk   : in std_logic;

    Result_Sel         : in  std_logic_vector(0 to 1);
    Mul_Result         : in  std_logic;
    Other_Result       : in  std_logic;
    ALU_Result         : in  std_logic;
    Shift_Logic_Result : in  std_logic;
    Data_Read          : in  std_logic;
    Data_Read_Mask     : in  std_logic;
    EX_Result          : out std_logic;
    New_Reg_Value      : out std_logic
    );

end entity Result_Mux_Bit;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

library Unisim;
use Unisim.vcomponents.all;

architecture IMP of Result_Mux_Bit is

  signal mul_ALU_Res    : std_logic;
  signal data_Shift_Res : std_logic;
  signal ex_Result_I    : std_logic;
  
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- architecture IMP

  -----------------------------------------------------------------------------
  -- Result bit
  -- The output of Other_Result and Mul_Result is '0' when not used so they can
  -- be ored together
  --
  -- mul_ALU_Res <= Mul_Result or Other_Result or (ALU_Result and not ResulSel(1)
  --
  --           Mul Other
  --            00 01 11 10
  -- ALU Sel 00  0  0  0  0  0000
  --         01  0  1  1  1  1110
  --         11  0  1  1  1  1110
  --         10  1  1  1  1  1111
  --
  -- INIT = 1110 1111 1110 0000 = EFE0
  -----------------------------------------------------------------------------
  Mul_ALU_Mux : LUT4                       -- Init Value for a Mux is 00CA
    generic map(
      INIT => X"EFE0"
      )
    port map (
      O  => mul_ALU_Res,                   -- [out]
      I0 => Other_Result,                  -- [in]
      I1 => Mul_Result,                    -- [in]
      I2 => Result_Sel(Result_Sel'right),  -- [in]
      I3 => ALU_Result);                   -- [in]

  -----------------------------------------------------------------------------
  -- Special function done on the Data_Read and Shift_Res (Shift_Logic_Result) inputs
  --
  -- For byte load the result bits(0:23) is '0'
  -- For halfword load the result bits(0:15) is '0'
  -- For Sex8 operation the result bits(0:23) is Op1(24)
  -- For Sext16 operation the result bits(0:15) is Op1(16)
  -- 
  -- This is done by actually masking the Result bit in the Mux function
  -- So the actual equation is
  -- Data_Shift_Res <= Data_Mask and ((Result_Sel(0) and Data_Read) or
  --                                   not(Result_Sel(0)) and (Shift_Res))
  --
  --                            bit 1,0
  --   bit3,2            Shift_Res Result_Sel
  -- Data_Read Mask      00  01  11  10
  --                 00   0   0   0   0   0000
  --                 01   0   0   0   1   0100
  --                 11   0   1   1   1   1110
  --                 10   0   0   0   0   0000
  -- Init Value := 1110 0000 0100 0000  (E040)
  -----------------------------------------------------------------------------
  Data_Shift_Mux : LUT4
    generic map(
      INIT => X"E040"
      )
    port map (
      O  => data_Shift_Res,                -- [out]
      I0 => Result_Sel(Result_Sel'right),  -- [in]
      I1 => Shift_Logic_Result,            -- [in]
      I2 => Data_Read_Mask,                -- [in]
      I3 => Data_Read);                    -- [in]

  Result_MUXF5 : MUXF5
    port map (
      I0 => mul_ALU_Res,                  -- [in]
      I1 => data_Shift_Res,               -- [in]
      S  => Result_Sel(Result_Sel'left),  -- [in]
      O  => ex_Result_I);                 -- [out]

  EX_Result <= ex_Result_I;
  
  EX_Result_DFF: FD
    port map (
      Q  => New_Reg_Value,
      D  => ex_Result_I,
      C  => Clk
      );
  
end architecture IMP;