data_flow.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

        Clk               => Clk,       -- [in  std_logic] Clock
        Reset             => reset_i,   -- [in  std_logic] Reset
        OF_PipeRun        => OF_PipeRun,  -- [in  boolean] Move the operand fetch stage
        EX_PipeRun        => true,      -- [in  boolean] Move the execute stage
        MEM_PipeRun       => true,      -- [in  boolean] Move the memory stage
        EX_Op1            => Op1_i,     -- [in  DATA_TYPE] First operand
        EX_Op2            => Op2_C,     -- [in  DATA_TYPE] Second operand
        EX_FPU_Op         => FPU_Op,    -- [in  FPU_OP_TYPE] FPU operation
        EX_FPU_Cond       => FPU_Cond,  -- [in  FPU_COND_TYPE] FPU comparison conditions
        EX_MTS_FSR        => fsr_Write_i,  -- [in  std_logic] MTS write to FSR
        EX_Start_FPU      => start_fpu_i,  -- [in  boolean] Start the FPU
        EX_Not_FPU_Instr  => Not_FPU_Instr,  -- [in  boolean] Not an FPU instruction
        MEM_Not_FPU_Instr => Not_FPU_Instr,  -- [in  boolean] Not an FPU instruction
        MEM_Sel_SPR_FSR   => true,  -- [in  boolean] Select SPR floating point status register
        MEM_FPU_Done      => fpu_done_i,  -- [out rboolean] FPU is finished in the next cycle
        MEM_FPU_Stall     => open,  -- [out rboolean] FPU is stalling Mem Stage
        MEM_FPU_Excep     => fpu_excep_i,  -- [out rboolean] FPU Exception
        WB_FPU_Excep      => open,      -- [out rboolean] FPU Exception
        WB_FPU_Result     => FPU_Result,  -- [out DATA_TYPE] FPU Result

        WB_FSR => FSR);   -- [out FSR_TYPE] FPU Status Register

    Hold_Exception_until_next_ofpiperun: process (Clk) is
    begin  -- process Hold_Exception_until_next_ofpiperun
      if Clk'event and Clk = '1' then     -- rising clock edge
        if OF_PipeRun then               -- synchronous reset (active high)
          hold_fpu_excep <= false;
        elsif (fpu_excep_i) then
          hold_fpu_excep <= true;        
        end if;
      end if;
    end process Hold_Exception_until_next_ofpiperun;

    fsr_Write_i <= '1' when FSR_Write else '0';
    start_fpu_i   <= (Start_FPU = '1');
    not_FPU_Instr <= (Not_FPU_Op = '1');
    fpu_done      <= '1' when fpu_done_i else '0';
    FPU_Excep     <= '1' when fpu_excep_i or hold_fpu_excep else '0';
    
  end generate Using_FPU;

  
  
  -- FPU doesn't exists for RTL targets
  No_FPU : if (not USE_FPU) generate
    FPU_Result <= (others => '0');
    FPU_Done   <= '0';
    FPU_Excep  <= '0';
    FSR        <= (others => '0');
  end generate No_FPU;
  
  Using_Debug : if (C_DEBUG_ENABLED = 1) generate

    No_Other_Units : if ((C_USE_BARREL = 0) and (C_USE_DIV = 0) and (not USE_FPU)) generate
      Other_Result <= FSL_Get_Data;
    end generate No_Other_Units;

    Using_Other_Units : if ((C_USE_BARREL = 1) or (C_USE_DIV = 1) or (USE_FPU)) generate
    begin
      other_Result <= (FSL_Get_Data or barrel_Result or div_result or FPU_Result);
    end generate Using_Other_Units;
    
  end generate Using_Debug;

  Not_Using_Debug : if (C_DEBUG_ENABLED /= 1) generate
    other_Result <= barrel_Result or div_result or FSL_Get_Data or FPU_Result;
  end generate Not_Using_Debug;

  -- instance "MUL_Unit_I"
  mul_unit_I: mul_unit
    generic map (
      C_TARGET     => C_TARGET,         -- [TARGET_FAMILY_TYPE]
      C_USE_HW_MUL => C_USE_HW_MUL,     -- [boolean] Hardware multiplier
      C_USE_MUL64  => C_USE_MUL64)      -- [boolean] 64 bit result
    port map (
      Clk             => Clk,           -- [in  std_logic] Clock
      Reset           => reset_i,       -- [in  std_logic] Reset
      EX_Not_Mul_Op   => EX_Not_Mul_Op,  -- [in  boolean] Disable multiplier
      MEM_Not_Mul_Op  => EX_Not_Mul_Op,  -- [in  boolean] Disable multiplier
      EX_Mulh_Instr   => EX_Mulh_Instr,  -- [in  boolean] Multiply high instruction
      EX_Mulhu_Instr  => EX_Mulhu_Instr,  -- [in  boolean] Unsigned multiply high instruction
      EX_Mulhsu_Instr => EX_Mulhsu_Instr,  -- [in  boolean] Signed*Unsigned multiply high instruction
      EX_Op1          => reg1,   -- [in  DATA_TYPE] Execute stage operand 1
      EX_Op2          => op2_C,  -- [in  DATA_TYPE] Execute stage operand 2
      EX_PipeRun      => true,          -- [in  boolean] Move the execute stage
      MEM_PipeRun     => true,          -- [in  boolean] Move the memory stage
      WB_Mul_Result   => mul_Result);  -- [out DATA_TYPE] WB stage multiplier result
  
  -----------------------------------------------------------------------------
  -- Result Mux
  -----------------------------------------------------------------------------

  Result_Mux_I : Result_Mux
    generic map (
      C_DATA_SIZE => C_DATA_SIZE,       -- [natural range 4 to 64]
      C_TARGET    => C_TARGET           -- [TARGET_FAMILY_TYPE]
      )
    port map (
      Clk                => Clk,        -- [in  std_logic]
      Reset              => Reset,      -- [in  boolean]
      Result_Sel         => result_Sel, -- [in  std_logic_vector(0 to 1)]
      Doublet_Read       => Doublet_Read,  -- [in  boolean]
      Quadlet_Read       => Quadlet_Read,  -- [in  boolean]
      -- Hexlet_Read        => Hexlet_Read,   -- [in  boolean]
      Sext8              => sext8_i,    -- [in  boolean]
      Sext16             => sext16_i,   -- [in  boolean]
      -- Sext32             => sext32_i,   -- [in  boolean]
      PCMP_Instr         => pcmp_instr_i,-- [in  boolean]
      Op1                => op1_i,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Mul_Result         => mul_or_PVR_Result,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Other_Result       => other_Result,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      ALU_Result         => alu_Result,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Shift_Logic_Result => shift_Logic_Result,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Data_Read          => Data_Read,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      EX_Result          => ex_Result,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      New_Reg_Value      => New_Reg_Value);  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]

  -- instance "Zero_Detect_I"
  Zero_Detect_I : Zero_Detect
    generic map (
      C_DATA_SIZE => C_DATA_SIZE,       -- [natural range 4 to 64]
      C_TARGET    => C_TARGET           -- [TARGET_FAMILY_TYPE]
      )
    port map (
      Reg_Test_Equal   => Reg_Test_Equal,    -- [in  std_logic]
      Reg_Test_Equal_N => Reg_Test_Equal_N,  -- [in  std_logic]
      EX_Result        => reg1,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Reg_Zero         => Reg_Zero_i);  -- [out std_logic]

  Reg_Zero <= Reg_Zero_i;
  Reg_neg  <= reg1(0);

  -----------------------------------------------------------------------------
  -- MSR
  -----------------------------------------------------------------------------

  -- instance "MSR_Reg_I"
  MSR_Reg_I : MSR_Reg
    generic map (
      C_TARGET         => C_TARGET,         -- [TARGET_FAMILY_TYPE]
      C_RESET_MSR      => C_RESET_MSR,      -- [MSR_REG_TYPE]
      C_PVR            => C_PVR,            -- [integer]
      C_USE_DIV        => C_USE_DIV_bool,   -- [boolean]
      C_USE_D_OPB      => USE_D_OPB,        -- [boolean]
      C_FSL_LINKS      => C_FSL_LINKS,      -- [integer]
      C_USE_ICACHE     => USE_ICACHE,       -- [boolean]
      C_USE_DCACHE     => USE_DCACHE,       -- [boolean]
      C_DATA_SIZE      => C_DATA_SIZE,      -- [natural]
      C_USE_MSR_INSTR  => C_USE_MSR_INSTR,  -- [integer]
      C_USE_EXCEPTIONS => C_USE_EXCEPTIONS  -- [boolean]
      )
    port map (
      Clk                => Clk,        -- [in  std_logic]
      Reset              => Reset,      -- [in  boolean]
      Write_Carry        => Write_Carry,         -- [in  boolean]
      New_Carry          => New_Carry,  -- [in  std_logic]
      MTS_Write          => MTSMSR_Write,        -- [in  boolean]
      Disable_Interrupts => Disable_Interrupts,  -- [in  boolean]
      Enable_Interrupts  => Enable_Interrupts,   -- [in  boolean]
      FSL_Write_Carry    => EX_FSL_Write_Carry,     -- [in  std_logic]
      FSL_Carry          => EX_FSL_Carry,  -- [in  std_logic]
      Set_FSL_Error      => Set_FSL_Error,       -- [in  boolean]
      Div_By_Zero        => Div_By_Zero_i,         -- [in std_logic]
      Set_BIP            => Set_BIP,    -- [in  boolean]
      Reset_BIP          => Reset_BIP,  -- [in  boolean]
      Disable_Exceptions => Disable_Exceptions,  -- [in  boolean]
      Enable_Exceptions  => Enable_Exceptions,   -- [in  boolean]
      Set_EIP            => Set_EIP,    -- [in  boolean]
      Reset_EIP          => Reset_EIP,  -- [in  boolean]
      Op1                => op1_i(C_DATA_SIZE-MSR_REG_TYPE'length to C_DATA_SIZE-1),
      Op2                => op2_C(C_DATA_SIZE-MSR_REG_TYPE'length to C_DATA_SIZE-1),
      MSRxxx_Instr       => MSRxxx_Instr,
      MSRclr_Instr       => MSRclr_Instr,
      MSR                => msr_I);     -- [out std_logic_vector(0 to 6)]

  MSR <= msr_I;
  
  Set_FSL_Error <= (EX_FSL_Control_Error = '1');

  -- Bit 31
  Enable_BusLock     <= (msr_I(MSR_BE_POS) = '1');
  Enable_Interrupt   <= (msr_I(MSR_IE_POS) = '1');
  Carry              <= msr_I(MSR_C_POS);
  BIP_Active         <= (msr_I(MSR_BIP_POS) = '1');
  -- Bit 27 is FSL error
  ICache_Enabled     <= (msr_I(MSR_ICE_POS) = '1');
  -- Bit 25 is Division by zero
  DCache_Enabled     <= (msr_I(MSR_DCE_POS) = '1');
  Exceptions_Enabled <= (msr_I(MSR_EE_POS) = '1');
  EIP_Active         <= (msr_I(MSR_EIP_POS) = '1');
  -- Bit 22

  -----------------------------------------------------------------------------
  -- PC Module
  -----------------------------------------------------------------------------

  PC_OF <= pc_OF_I;

  PC_Module_I : PC_Module
    generic map (
      C_DATA_SIZE     => C_DATA_SIZE,   -- [natural range 4 to 64]
      C_TARGET        => C_TARGET,      -- [Target_Family_type]
      C_PC_START_ADDR => C_PC_START_ADDR  -- [string]
      )
    port map (
      Clk              => Clk,          -- [in  std_logic]
      Reset            => Reset,        -- [in  boolean]
      Stop_Instr_Fetch => Stop_Instr_Fetch,
      OF_PipeRun       => OF_PipeRun,   -- [in  boolean]
      PC_Incr          => PC_Incr,      -- [in  boolean]
      Jump             => Jump,         -- [in  boolean]
      ALU_Result       => alu_Result,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      PC_Write         => PC_Write,     -- [in  boolean]
      IReady           => IReady,       -- [in  std_logic]
      Buffer_Addr      => Buffer_Addr,  -- [in  std_logic_vector(0 to 3)]
      PC_OF            => pc_OF_I,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      PC_EX            => pc_EX,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      Instr_Addr       => Instr_Addr);  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]


  -----------------------------------------------------------------------------
  -- PVR Module
  -----------------------------------------------------------------------------

  PVR_I : PVR 
  generic map(
    C_PVR                   => C_PVR, 
    C_MB_VERSION            => C_MB_VERSION, 
    C_PVR_USER1             => C_PVR_USER1, 
    C_PVR_USER2             => C_PVR_USER2, 
    C_D_OPB                 => C_D_OPB,
    C_D_LMB                 => C_D_LMB,
    C_I_OPB                 => C_I_OPB,
    C_I_LMB                 => C_I_LMB,
    C_INTERRUPT_IS_EDGE     => C_INTERRUPT_IS_EDGE,
    C_EDGE_IS_POSITIVE      => C_EDGE_IS_POSITIVE,
    C_D_PLB                 => C_D_PLB,
    C_I_PLB                 => C_I_PLB,
    C_INTERCONNECT          => C_INTERCONNECT,
    C_USE_MSR_INSTR         => C_USE_MSR_INSTR_bool,
    C_USE_PCMP_INSTR        => C_USE_PCMP_INSTR,
    C_AREA_OPTIMIZED        => true,
    C_USE_BARREL            => C_USE_BARREL_bool,
    C_USE_DIV               => C_USE_DIV_bool,
    C_USE_HW_MUL            => C_USE_HW_MUL,
    C_USE_FPU               => C_USE_FPU,
    C_USE_MUL64             => C_USE_MUL64,
    C_IPLB_BUS_EXCEPTION    => C_IPLB_BUS_EXCEPTION,
    C_DPLB_BUS_EXCEPTION    => C_DPLB_BUS_EXCEPTION,
    C_OPCODE_0x0_ILLEGAL    => C_OPCODE_0x0_ILLEGAL,
    C_UNALIGNED_EXCEPTIONS  => C_UNALIGNED_EXCEPTIONS,
    C_ILL_OPCODE_EXCEPTION  => C_ILL_OPCODE_EXCEPTION,
    C_IOPB_BUS_EXCEPTION    => C_IOPB_BUS_EXCEPTION,
    C_DOPB_BUS_EXCEPTION    => C_DOPB_BUS_EXCEPTION,
    C_DIV_ZERO_EXCEPTION    => C_DIV_ZERO_EXCEPTION,
    C_FPU_EXCEPTION         => C_FPU_EXCEPTION,
    C_FSL_EXCEPTION         => C_FSL_EXCEPTION,
    C_USE_EXTENDED_FSL_INSTR  => C_USE_EXTENDED_FSL_INSTR,
    C_DEBUG_ENABLED         => C_DEBUG_ENABLED, 
    C_NUMBER_OF_PC_BRK      => C_NUMBER_OF_PC_BRK, 
    C_NUMBER_OF_RD_ADDR_BRK => C_NUMBER_OF_RD_ADDR_BRK, 
    C_NUMBER_OF_WR_ADDR_BRK => C_NUMBER_OF_WR_ADDR_BRK, 
    C_FSL_LINKS             => C_FSL_LINKS, 
    C_USE_ICACHE            => C_USE_ICACHE, 
    C_ADDR_TAG_BITS         => C_ADDR_TAG_BITS, 
    C_ICACHE_USE_FSL        => C_ICACHE_USE_FSL, 
    C_ALLOW_ICACHE_WR       => C_ALLOW_ICACHE_WR, 
    C_ICACHE_LINE_LEN       => C_ICACHE_LINE_LEN, 
    C_CACHE_BYTE_SIZE       => C_CACHE_BYTE_SIZE, 
    C_ICACHE_ALWAYS_USED    => C_ICACHE_ALWAYS_USED,
    C_USE_DCACHE            => C_USE_DCACHE, 
    C_DCACHE_ADDR_TAG       => C_DCACHE_ADDR_TAG, 
    C_DCACHE_USE_FSL        => C_DCACHE_USE_FSL, 
    C_ALLOW_DCACHE_WR       => C_ALLOW_DCACHE_WR, 
    C_DCACHE_LINE_LEN       => C_DCACHE_LINE_LEN, 
    C_DCACHE_BYTE_SIZE      => C_DCACHE_BYTE_SIZE, 
    C_DCACHE_ALWAYS_USED    => C_DCACHE_ALWAYS_USED,
    C_ICACHE_BASEADDR       => C_ICACHE_BASEADDR, 
    C_ICACHE_HIGHADDR       => C_ICACHE_HIGHADDR, 
    C_DCACHE_BASEADDR       => C_DCACHE_BASEADDR, 
    C_DCACHE_HIGHADDR       => C_DCACHE_HIGHADDR, 
    C_TARGET                => C_TARGET, 
    C_USE_MMU               => C_USE_MMU,
    C_MMU_DTLB_SIZE         => C_MMU_DTLB_SIZE,
    C_MMU_ITLB_SIZE         => C_MMU_ITLB_SIZE,
    C_MMU_TLB_ACCESS        => C_MMU_TLB_ACCESS,
    C_MMU_ZONES             => C_MMU_ZONES,
    C_RESET_MSR             => C_RESET_MSR
    )
  port map (
    -- Common signals.
    Clk             => Clk,
    Reset           => Reset_i,
    
    -- PVR read interface.
    MEM_PipeRun     => true,
    MEM_PVR_Select  => MEM_PVR_Select,
    MEM_Sel_SPR_PVR => MEM_Sel_SPR_PVR,
    WB_Sel_SPR_PVR  => MEM_Sel_SPR_PVR,
    WB_PVR          => WB_PVR
    );

  -----------------------------------------------------------------------------
  -- FSL Module
  -----------------------------------------------------------------------------
  
  -- This check is needed for simulation otherwise one can get errors like:
  -- ** Fatal: (vsim-3421) Value 7 is out of range 0 to 2
  EX_FSL_No_for_simulation: process (Op2_i) is
  begin  -- process Process_Only_For_Simulation
    -- pragma translate_off
    if (unsigned(Op2_i(DATA_SIZE-log2(C_MAX_FSL_LINKS) to DATA_SIZE-1)) < C_FSL_LINKS) then
    -- pragma translate_on
      FSL_No <= to_integer(unsigned(Op2_i(DATA_SIZE-log2(C_MAX_FSL_LINKS) to DATA_SIZE-1)));
    -- pragma translate_off
    else
      FSL_No <= 0;
    end if;
    -- pragma translate_on
  end process EX_FSL_No_for_simulation;

  -- FSL output
  FSL_Get_No    <= FSL_No;
  FSL_Put_No    <= FSL_No;
  FSL_Put_Data  <= reg1;
  

  -----------------------------------------------------------------------------
  -- Result creation
  -----------------------------------------------------------------------------

  mul_or_PVR_Result <= mul_Result or WB_PVR when C_PVR > 0 else
                       mul_Result;

  -----------------------------------------------------------------------------
  -- Output renaming
  -----------------------------------------------------------------------------

  Data_Addr <= alu_Result;

  Op1_Low <= Op1_i(C_DATA_SIZE-2 to C_DATA_SIZE-1);
  Op2_Low <= Op2_i(C_DATA_SIZE-2 to C_DATA_SIZE-1);

  Op1 <= Op1_i;
  Op2 <= Op2_i;
  
  
end architecture IMP;