data_flow.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      Reg_Zero    : in  std_logic;
      Unsigned_op : in  std_logic;
      Op1         : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Op2         : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Div_Result  : out std_logic_vector(0 to C_DATA_SIZE-1);
      Div_By_Zero : out std_logic;
      Div_Done    : out std_logic);
  end component Div_unit;
  
  component FPU is
    generic (
      C_TARGET        : TARGET_FAMILY_TYPE;
      C_USE_FPU       : integer;  -- Enable FPU?
      C_FPU_EXCEPTION : integer);
    port (
      Clk               : in  std_logic;      -- Clock
      Reset             : in  std_logic;      -- Reset
      OF_PipeRun        : in  boolean;  -- Move the operand fetch stage
      EX_PipeRun        : in  boolean;  -- Move the execute stage
      MEM_PipeRun       : in  boolean;  -- Move the memory stage
      EX_Op1            : in  DATA_TYPE;      -- First operand
      EX_Op2            : in  DATA_TYPE;      -- Second operand
      EX_FPU_Op         : in  FPU_OP_TYPE;    -- FPU operation
      EX_FPU_Cond       : in  FPU_COND_TYPE;  -- FPU comparison conditions
      EX_MTS_FSR        : in  std_logic;      -- MTS write to FSR
      EX_Start_FPU      : in  boolean;  -- Start the FPU
      EX_Not_FPU_Instr  : in  boolean;  -- Not an FPU instruction
      MEM_Not_FPU_Instr : in  boolean;  -- Not an FPU instruction
      MEM_Sel_SPR_FSR   : in  boolean;  -- Select SPR floating point status register
      MEM_FPU_Done      : out rboolean;  -- FPU is finished in the next cycle
      MEM_FPU_Stall     : out rboolean;  -- FPU is stalling Mem Stage
      MEM_FPU_Excep     : out rboolean;  -- FPU Exception
      WB_FPU_Excep      : out rboolean;  -- FPU Exception
      WB_FPU_Result     : out DATA_TYPE;      -- FPU Result
      WB_FSR            : out FSR_TYPE);      -- FPU Status Register
  end component FPU;
  
  component PVR is
  generic (
    -- PVR0 Basic
    C_PVR                   : integer;   -- Which PVR mode None=0, Basic=1, Full=2
    C_MB_VERSION            : std_logic_vector(0 to 7);
    C_PVR_USER1             : std_logic_vector(0 to 7);   -- User defined byte
    -- PVR1 User defined
    C_PVR_USER2             : std_logic_vector(0 to 31);   -- User defined word
    -- PVR2 Configuration
    C_D_OPB                 : integer;
    C_D_LMB                 : integer;
    C_I_OPB                 : integer;
    C_I_LMB                 : integer;
    C_INTERRUPT_IS_EDGE     : integer;
    C_EDGE_IS_POSITIVE      : integer;
    C_D_PLB                 : integer;
    C_I_PLB                 : integer;
    C_INTERCONNECT          : integer;
    C_USE_MSR_INSTR         : boolean;
    C_USE_PCMP_INSTR        : boolean;
    C_AREA_OPTIMIZED        : boolean;
    C_USE_BARREL            : boolean;
    C_USE_DIV               : boolean;
    C_USE_HW_MUL            : boolean;
    C_USE_FPU               : integer;
    C_USE_MUL64             : boolean;
    C_IPLB_BUS_EXCEPTION    : integer;
    C_DPLB_BUS_EXCEPTION    : integer;
    C_OPCODE_0x0_ILLEGAL    : integer;
    C_UNALIGNED_EXCEPTIONS  : integer;
    C_ILL_OPCODE_EXCEPTION  : integer;
    C_IOPB_BUS_EXCEPTION    : integer;
    C_DOPB_BUS_EXCEPTION    : integer;
    C_DIV_ZERO_EXCEPTION    : integer;
    C_FPU_EXCEPTION         : integer;
    C_FSL_EXCEPTION         : integer;
    C_USE_EXTENDED_FSL_INSTR  : integer;
    -- PVR3 Debug and FSL
    C_DEBUG_ENABLED         : integer;
    C_NUMBER_OF_PC_BRK      : integer;
    C_NUMBER_OF_RD_ADDR_BRK : integer;
    C_NUMBER_OF_WR_ADDR_BRK : integer;
    C_FSL_LINKS             : integer;
    -- PVR4 Instruction Cache
    C_USE_ICACHE            : integer;
    C_ADDR_TAG_BITS         : integer;
    C_ICACHE_USE_FSL        : integer;
    C_ALLOW_ICACHE_WR       : integer;
    C_ICACHE_LINE_LEN       : integer;
    C_CACHE_BYTE_SIZE       : integer;
    C_ICACHE_ALWAYS_USED    : integer;
    -- PVR5 Data Cache 
    C_USE_DCACHE            : integer;
    C_DCACHE_ADDR_TAG       : integer;
    C_DCACHE_USE_FSL        : integer;
    C_ALLOW_DCACHE_WR       : integer;
    C_DCACHE_LINE_LEN       : integer;
    C_DCACHE_BYTE_SIZE      : integer;
    C_DCACHE_ALWAYS_USED    : integer;
    -- PVR6 Instruction Cache Base Address
    C_ICACHE_BASEADDR       : std_logic_vector(0 to 31);
    -- PVR7 Instruction Cache High Address
    C_ICACHE_HIGHADDR       : std_logic_vector(0 to 31);
    -- PVR8 Data Cache Base Address
    C_DCACHE_BASEADDR       : std_logic_vector(0 to 31);
    -- PVR9 Data Cache High Address
    C_DCACHE_HIGHADDR       : std_logic_vector(0 to 31);
    -- PVR10 Target
    C_TARGET                : TARGET_FAMILY_TYPE;
    -- PVR11 MMU and reset value for MSR register
    C_USE_MMU               : integer;
    C_MMU_DTLB_SIZE         : integer;
    C_MMU_ITLB_SIZE         : integer;
    C_MMU_TLB_ACCESS        : integer;
    C_MMU_ZONES             : integer;
    C_RESET_MSR             : std_logic_vector(MSR_REG_POS_TYPE)
    );
  port (
    -- Common signals.
    Clk             : in  std_logic;
    Reset           : in  std_logic;
    
    -- PVR read interface.
    MEM_PipeRun     : in  boolean;                   -- Move the memory stage
    MEM_PVR_Select  : in  std_logic_vector(0 to 3);  -- Select which PVR to read
    MEM_Sel_SPR_PVR : in  boolean;                   -- Select SPR processor version register
    WB_Sel_SPR_PVR  : in  boolean;                   -- Select SPR processor version register
    WB_PVR          : out PVR_TYPE                   -- PVR Read port 
    );
  end component PVR;

  attribute syn_keep          : boolean;
  attribute syn_keep of op2_i : signal is true;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- architecture IMP

  reset_i <= '1' when Reset else '0';
    
  -----------------------------------------------------------------------------
  -- Component instantiations
  -----------------------------------------------------------------------------
  Reg_File_Dbg : if (C_DEBUG_ENABLED = 1) generate
    write_addr_I    <= Write_Addr;
    reg_write_I     <= Reg_Write when (Dbg_Inhibit_EX = '0') else false;
    not_Barrel_Op_i <= Not_Barrel_Op or Dbg_Inhibit_EX;
    EX_not_Mul_Op_i <= EX_Not_Mul_Op or (Dbg_Inhibit_EX = '1');
    not_Div_Op_i    <= Not_Div_Op or Dbg_Inhibit_EX;
    not_FPU_Op_i    <= Not_FPU_Op or Dbg_Inhibit_EX;
    compare_Instr_i <= Compare_Instr and not Dbg_Inhibit_EX;
    sext8_i         <= sext8 and (Dbg_Inhibit_EX = '0');
    sext16_i        <= sext16 and (Dbg_Inhibit_EX = '0');
    -- sext32_i        <= sext32 and (Dbg_Inhibit_EX = '0');
    pcmp_instr_i    <= PCMP_Instr and (Dbg_Inhibit_EX = '0');
  end generate Reg_File_Dbg;

  No_Reg_File_Dbg : if (C_DEBUG_ENABLED = 0) generate
    write_addr_I    <= Write_Addr;
    reg_write_I     <= Reg_Write;
    not_Barrel_Op_i <= Not_Barrel_Op;
    EX_not_Mul_Op_i <= EX_Not_Mul_Op;
    not_Div_Op_i    <= Not_Div_Op;
    not_FPU_Op_i    <= Not_FPU_Op;
    compare_Instr_i <= Compare_Instr;
    sext8_i         <= sext8;
    sext16_i        <= sext16;
    -- sext32_i        <= sext32;
    pcmp_instr_i    <= PCMP_Instr;
  end generate No_Reg_File_Dbg;

  -- instance "Register_File_I"
  Register_File_I : Register_File
    generic map (
      C_DATA_SIZE => C_DATA_SIZE,       -- [natural range 4 to 64]
      C_TARGET    => C_TARGET           -- [TARGET_FAMILY_TYPE]
      )
    port map (
      Clk        => Clk,                -- [in  std_logic]
      Reset      => Reset,              -- [in  boolean]
      Write_Addr => write_Addr_I,       -- [in  std_logic_vector(0 to 4)]
      Reg1_Addr  => Reg1_Addr,          -- [in  std_logic_vector(0 to 4)]
      Reg2_Addr  => Reg2_Addr,          -- [in  std_logic_vector(0 to 4)]
      Reg_Write  => reg_Write_I,        -- [in  boolean]
      EX_Result  => ex_Result,   -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Data_Write => Data_Write_i,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      Reg1_Data  => reg1_Data,   -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      Reg2_Data  => reg2_Data);  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]

  Data_Write <= Data_Write_i;

  -- instance "Operand_Select_I"
  Operand_Select_I : Operand_Select
    generic map (
      C_DATA_SIZE      => C_DATA_SIZE,  -- [natural range 4 to 64]
      C_DEBUG_ENABLED  => C_DEBUG_ENABLED,
      C_PVR            => C_PVR,
      C_FSL_EXCEPTION  => FSL_EXCEPTION_ON,
      C_USE_EXCEPTIONS => C_USE_EXCEPTIONS,
      C_USE_FPU_bool   => USE_FPU,
      C_TARGET         => C_TARGET,     -- [TARGET_FAMILY_TYPE]
      C_INTERRUPT_ADDR => C_INTERRUPT_ADDR,  -- [string]
      C_EXT_BRK_ADDR   => C_EXT_BRK_ADDR,  -- [string]
      C_EXCEPTION_ADDR => C_EXCEPTION_ADDR   -- [string]
      )
    port map (
      Clk                     => Clk,   -- [in  std_logic]
      Reset                   => Reset,  -- [in  boolean]
      OF_PipeRun              => OF_PipeRun,               -- [in  boolean]
      Reg1_Data               => reg1_Data,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Reg2_Data               => reg2_Data,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Imm_Value               => Imm_Value,  -- [in  std_logic_vector(0 to 15)]
      MSR                     => msr_I,  -- [in  std_logic_vector(0 to 7)]
      PC_OF                   => pc_OF_I,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      EX_Result               => ex_Result,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      OpSel1_PC               => OpSel1_PC,  -- [in  boolean]
      OpSel1_SPR              => OpSel1_SPR,               -- [in  boolean]
      OpSel2_Imm              => OpSel2_Imm,               -- [in  boolean]
      Take_Ext_BRK            => Take_Ext_BRK,             -- [in  boolean]
      Take_Exception          => Take_Exception,           -- [in  boolean]
      Take_Interrupt          => Take_Interrupt,           -- [in  boolean]
      Store_PC_For_Intr       => Store_PC_For_Intr,        -- [in  boolean]
      Store_PC_For_Intr_NoImm => Store_PC_For_Intr_NoImm,  -- [in  boolean]
      Res_Forward1            => Res_Forward1,             -- [in  boolean]
      Res_Forward2            => Res_Forward2,             -- [in  boolean]
      Imm_Instr               => Imm_Instr,  -- [in  boolean]
      Use_Imm_Reg             => Use_Imm_Reg,              -- [in  boolean]
      -- OpSel1_FSR              => OpSel1_FSR,               -- [in  boolean]
      FSR                     => FSR,   -- [in std_logic_vector(0 to 4)]
      Reg1                    => reg1,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      Op1                     => op1_i,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      Op2                     => op2_i,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      Op2_C                   => op2_C,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      MFS_Reg_Sel             => MFS_Reg_Sel,
      BTR                     => BTR,
      EAR                     => EAR,
      EDR                     => EDR,
      ESR                     => ESR,
      word_r1_r2_unalignment  => word_r1_r2_unalignment,   -- [out  std_logic]
      word_r1_imm_unalignment => word_r1_imm_unalignment,  -- [out  std_logic]
      halfword_unalignment    => halfword_unalignment      -- [out  std_logic]
      );

  -- instance "ALU_I"
  EX_CMP_Op       <= Compare_Instr_i = '1';
  EX_Unsigned_Op  <= Unsigned_Op = '1';

  ALU_I : ALU
    generic map (
      C_AREA_OPTIMIZED     => C_AREA_OPTIMIZED,
      C_TARGET => C_TARGET              -- [TARGET_FAMILY_TYPE]
    )
    port map (
      EX_ALU_Op      => ALU_Op,       -- [in  slv_0to1]
      EX_CMP_Op      => EX_CMP_Op,       -- [in  boolean]
      EX_Unsigned_Op => EX_Unsigned_Op,  -- [in  boolean]
      EX_Use_Carry   => true,
      
      EX_CarryIn => Carry_In,         -- [in  std_logic]
      EX_Op1     => op1_i,             -- [in  DATA_TYPE]
      EX_Op2     => op2_i,             -- [in  DATA_TYPE]

      EX_ALU_Result => alu_Result,  -- [out DATA_TYPE]
      EX_ALU_Carry  => ALU_Carry      -- [out std_logic]
    );

  -- instance "Shift_Logic_Module_I"
  Shift_Logic_Module_I : Shift_Logic_Module
    generic map (
      C_USE_PCMP_INSTR => C_USE_PCMP_INSTR,
      C_DATA_SIZE      => C_DATA_SIZE,  -- [natural range 1 to 64]
      C_TARGET         => C_TARGET      -- [Target_Family_TYPE]
      )
    port map (
      Op1                => op1_i,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Op2                => op2_i,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
      Shift_Carry_In     => Shift_Carry_In,      -- [in  std_logic]
      Sext8              => sext8,      -- [in  boolean]
      Sext16             => sext16,     -- [in  boolean]
      -- Sext32             => sext32,     -- [in  boolean]
      Sign_Extend        => Sign_Extend,   -- [in  boolean]
      Shift_Oper         => Shift_Oper,    -- [in  std_logic_vector(0 to 1)]
      Logic_Oper         => Logic_Oper,    -- [in  std_logic_vector(0 to 1)]
      PCMP_Instr         => pcmp_instr_i,  -- [in  boolean]
      Select_Logic       => Select_Logic,  -- [in  boolean]
      -- Logic_Result       => Logic_Result,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      Shift_Logic_Result => shift_Logic_Result,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
      Shift_Carry_Out    => Shift_Carry_Out);    -- [out std_logic]

  Using_Barrel_Shifter : if (C_USE_BARREL = 1) generate

    barrel_shift_I : barrel_shift
      generic map (
        C_DATA_SIZE => C_DATA_SIZE,     -- [natural range 4 to 64]
        C_TARGET    => C_TARGET         -- [TARGET_FAMILY_TYPE]
--        C_TARGET    => RTL         -- [TARGET_FAMILY_TYPE]
        )
      port map (
        Clk           => Clk,           -- [in  std_logic]
        Reset         => Reset,         -- [in  boolean]
        Op1           => Op1_i,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
        Not_Barrel_Op => not_Barrel_Op_i,  -- [in  std_logic]
        Left_Shift    => Left_Shift,    -- [in  std_logic]
        Arith_Shift   => Arith_Shift,   -- [in  std_logic]
        Shift         => op2_i(C_DATA_SIZE-6 to C_DATA_SIZE-1),  -- [in  std_logic_vector(0 to 5)]
        Barrel_Result => barrel_Result);  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]

  end generate Using_Barrel_Shifter;

  Not_Using_Barrel : if (C_USE_BARREL = 0) generate
    barrel_Result <= (others => '0');
  end generate Not_Using_Barrel;

  Using_Div_Unit : if (C_USE_DIV = 1) generate
    Div_unit_I1 : Div_unit
      generic map (
        C_TARGET    => C_TARGET,        -- [TARGET_FAMILY_TYPE]
        C_DATA_SIZE => C_DATA_SIZE)     -- [natural range 8 to 64]
      port map (
        Clk         => Clk,             -- [in  std_logic]
        Reset       => Reset,           -- [in  boolean]
        OF_PipeRun  => OF_PipeRun,      -- [in  boolean]
        Start_Div   => Start_Div,       -- [in  std_logic]
        Not_Div_Op  => not_Div_Op_i,    -- [in  std_logic]
        Reg_Zero    => Reg_Zero_i,      -- [in  std_logic]
        Unsigned_Op => Unsigned_Op,     -- [in  std_logic]
        Op1         => Op1_i,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
        Op2         => Op2_C,  -- [in  std_logic_vector(0 to C_DATA_SIZE-1)]
        Div_Result  => Div_Result,  -- [out std_logic_vector(0 to C_DATA_SIZE-1)]
        Div_By_Zero => Div_By_Zero_i,     -- [out std_logic]
        Div_Done    => Div_Done);       -- [out std_logic]
  end generate Using_Div_Unit;

  Not_Using_Div_Unit : if (C_USE_DIV /= 1) generate
    Div_Result    <= (others => '0');
    Div_Done      <= '0';
    Div_By_Zero_i <= '0';
  end generate Not_Using_Div_Unit;
  Div_By_Zero <= Div_By_Zero_i;

  -- FPU doesn't exists for RTL targets
  Using_FPU : if (USE_FPU) generate

    -- The order of Op2 and Op1 is intentional to match
    -- rsub, cmp, and idiv instructions
    FPU_I : FPU
      generic map (
        C_TARGET        => C_TARGET,    -- [TARGET_FAMILY_TYPE]
        C_USE_FPU       => C_USE_FPU,   -- [integer] Enable FPU?
        C_FPU_EXCEPTION => C_FPU_EXCEPTION)  -- [integer]
      port map (