data_flow.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  signal compare_Instr_i : std_logic;
  signal alu_Result      : std_logic_vector(0 to C_DATA_SIZE-1);
  signal EX_CMP_Op       : boolean;
  signal EX_Unsigned_Op  : boolean;

  -- outputs of "Shift_Logic_Module_I"
  signal shift_Logic_Result : std_logic_vector(0 to C_DATA_SIZE-1);
  -- signal Logic_Result       : std_logic_vector(0 to C_DATA_SIZE-1);

  -- outputs of "MUL_Unit_I"
  signal EX_not_Mul_Op_i : rboolean;
  signal mul_Result   : std_logic_vector(0 to C_DATA_SIZE-1);

  -- ports to "Barrel_Shifter_I"
  signal not_Barrel_Op_i : std_logic;
  signal barrel_Result   : std_logic_vector(0 to C_DATA_SIZE-1);

  signal other_Result : std_logic_vector(0 to C_DATA_SIZE-1);

  -- outputs of "Result_Mux_I"
  -- Resolved booleans
  signal sext8_i       : rboolean;
  signal sext16_i      : rboolean;

  -- signal sext32_i      : boolean;
  signal pcmp_instr_i  : rboolean;
  signal ex_Result     : std_logic_vector(0 to C_DATA_SIZE-1);
  signal Data_Write_i  : std_logic_vector(0 to C_DATA_SIZE-1);

  -- outputs of "MSR_Reg_I"
  signal msr_I       : MSR_REG_TYPE;

  -- outputs of "PC_Module_I"
  -- signal pc_Write_I : boolean;
  signal pc_OF_I    : std_logic_vector(0 to C_DATA_SIZE-1);

  -- Div unit signals
  signal not_Div_Op_i  : std_logic;
  signal Div_By_Zero_i : std_logic;
  signal Reg_Zero_i    : std_logic;                             -- [in]
  signal Div_Result    : std_logic_vector(0 to C_DATA_SIZE-1);  -- [out]

  -- FPU unit signals
  signal not_FPU_Op_i  : std_logic;
  signal FPU_Result    : std_logic_vector(0 to C_DATA_SIZE-1);  -- [out]
  signal FSR           : std_logic_vector(0 to 4);
  signal fpu_div_done  : boolean;
  signal fpu_done_i    : boolean;
  signal fpu_excep_i   : boolean;
  signal start_fpu_i   : boolean;
  signal not_FPU_Instr : boolean;
  signal fsr_Write_i   : std_logic;
  signal hold_fpu_excep : boolean;


  -- PVR signals and constants
  signal   WB_PVR               : PVR_TYPE;
  signal   mul_or_PVR_Result    : std_logic_vector(0 to C_DATA_SIZE-1);
  constant C_USE_BARREL_bool    : boolean := (C_USE_BARREL    > 0);
  constant C_USE_DIV_bool       : boolean := (C_USE_DIV       > 0);
  constant C_USE_MSR_INSTR_bool : boolean := (C_USE_MSR_INSTR > 0);

  signal reset_i : std_logic;

  -- MSR constants
  constant USE_D_OPB  : boolean := C_D_OPB = 1;  -- Not for C_D_PLB
  constant USE_ICACHE : boolean := C_USE_ICACHE = 1;
  constant USE_DCACHE : boolean := C_USE_DCACHE = 1;
  constant USE_FPU    : boolean := (C_USE_FPU /= 0);
  
  -----------------------------------------------------------------------------
  -- Component declarations
  -----------------------------------------------------------------------------

  component Register_File is
    generic (
      C_DATA_SIZE : natural range 4 to 64;
      C_TARGET    : TARGET_FAMILY_TYPE
      );
    port (
      Clk        : in  std_logic;
      Reset      : in  boolean;
      Write_Addr : in  std_logic_vector(0 to 4);
      Reg1_Addr  : in  std_logic_vector(0 to 4);
      Reg2_Addr  : in  std_logic_vector(0 to 4);
      Reg_Write  : in  boolean;
      EX_Result  : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
      Reg1_Data  : out std_logic_vector(0 to C_DATA_SIZE-1);
      Reg2_Data  : out std_logic_vector(0 to C_DATA_SIZE-1));
  end component Register_File;

  component Operand_Select is
    generic (
      -- Size generics
      C_DATA_SIZE      : natural range 4 to 64;
      C_DEBUG_ENABLED  : integer := 0;
      C_PVR            : integer := 0;
      C_FSL_EXCEPTION  : boolean := false;
      C_USE_EXCEPTIONS : boolean := false;
      C_USE_FPU_bool   : boolean := false;
      C_TARGET         : TARGET_FAMILY_TYPE;
      C_INTERRUPT_ADDR : string;
      C_EXT_BRK_ADDR   : string;
      C_EXCEPTION_ADDR : string
      );
    port (
      Clk   : in std_logic;
      Reset : in boolean;

      OF_PipeRun : in boolean;

      Reg1_Data : in std_logic_vector(0 to C_DATA_SIZE-1);
      Reg2_Data : in std_logic_vector(0 to C_DATA_SIZE-1);
      Imm_Value : in std_logic_vector(0 to 15);
      MSR       : in MSR_REG_TYPE;
      PC_OF     : in std_logic_vector(0 to C_DATA_SIZE-1);
      EX_Result : in std_logic_vector(0 to C_DATA_SIZE-1);

      OpSel1_PC      : in boolean;
      OpSel1_SPR     : in boolean;
      OpSel2_Imm     : in boolean;
      Take_Ext_BRK   : in boolean;
      Take_Exception : in boolean;
      Take_Interrupt : in boolean;
      Store_PC_For_Intr       : in boolean;
      Store_PC_For_Intr_NoImm : in boolean;
      Res_Forward1   : in boolean;
      Res_Forward2   : in boolean;
      Imm_Instr      : in boolean;
      Use_Imm_Reg    : in boolean;

      -- OpSel1_FSR : in boolean;
      FSR        : in std_logic_vector(0 to 4);

      Reg1  : out std_logic_vector(0 to C_DATA_SIZE-1);
      Op1   : out std_logic_vector(0 to C_DATA_SIZE-1);
      Op2   : out std_logic_vector(0 to C_DATA_SIZE-1);
      Op2_C : out std_logic_vector(0 to C_DATA_SIZE-1);

      MFS_Reg_Sel             : in  std_logic_vector(0 to 2);
      BTR                     : in  BTR_TYPE;
      EAR                     : in  EAR_TYPE;
      EDR                     : in  EDR_TYPE;
      ESR                     : in  ESR_TYPE;
      word_r1_r2_unalignment  : out std_logic;
      word_r1_imm_unalignment : out std_logic;
      halfword_unalignment    : out std_logic
      );
  end component Operand_Select;

  component ALU is
    generic (
      C_AREA_OPTIMIZED       : integer                := 0;
      C_TARGET :    TARGET_FAMILY_TYPE
    );
    port (
      EX_ALU_Op      : in slv_0to1;
      -- Compare_Instr  : in  std_logic;
      EX_CMP_Op : in boolean;
      EX_Unsigned_Op : in boolean;
      EX_Use_Carry   : in boolean;

      EX_CarryIn : in std_logic;
      EX_Op1     : in DATA_TYPE;
      EX_Op2     : in DATA_TYPE;

      EX_ALU_Result : out DATA_TYPE;
      EX_ALU_Carry  : out std_logic
    );
  end component ALU;

  component Shift_Logic_Module is
    generic (
      C_USE_PCMP_INSTR : boolean := true;
      C_DATA_SIZE   : natural range 1 to 64;
      C_TARGET    : TARGET_FAMILY_TYPE
      );
    port (
      Op1                : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Op2                : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Shift_Carry_In     : in  std_logic;
      Sext8              : in  boolean;
      Sext16             : in  boolean;
      -- Sext32             : in  boolean;
      Sign_Extend        : in  boolean;
      Shift_Oper         : in  std_logic_vector(0 to 1);
      Logic_Oper         : in  std_logic_vector(0 to 1);
      PCMP_Instr         : in  boolean;
      Select_Logic       : in  boolean;
      -- Logic_Result       : out std_logic_vector(0 to C_DATA_SIZE-1);
      Shift_Logic_Result : out std_logic_vector(0 to C_DATA_SIZE-1);
      Shift_Carry_Out    : out std_logic);
  end component Shift_Logic_Module;

  component mul_unit is
    generic (
      C_TARGET     : TARGET_FAMILY_TYPE;
      C_USE_HW_MUL : boolean;           -- Hardware multiplier
      C_USE_MUL64  : boolean);          -- 64 bit result
    port (
      Clk             : in  std_logic;   -- Clock
      Reset           : in  std_logic;   -- Reset
      EX_Not_Mul_Op   : in  boolean;     -- Disable multiplier
      MEM_Not_Mul_Op  : in  boolean;     -- Disable multiplier
      EX_Mulh_Instr   : in  boolean;     -- Multiply high instruction
      EX_Mulhu_Instr  : in  boolean;     -- Unsigned multiply high instruction
      EX_Mulhsu_Instr : in  boolean;     -- Signed*Unsigned multiply high instruction
      EX_Op1          : in  DATA_TYPE;   -- Execute stage operand 1
      EX_Op2          : in  DATA_TYPE;   -- Execute stage operand 2
      EX_PipeRun      : in  boolean;     -- Move the execute stage
      MEM_PipeRun     : in  boolean;     -- Move the memory stage
      WB_Mul_Result   : out DATA_TYPE);  -- WB stage multiplier result
  end component mul_unit;

  component barrel_shift is
    generic (
      C_DATA_SIZE : natural range 4 to 64;
      C_TARGET    : TARGET_FAMILY_TYPE
      );
    port (
      Clk           : in  std_logic;
      Reset         : in  boolean;
      Op1           : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Not_Barrel_Op : in  std_logic;
      Left_Shift    : in  std_logic;
      Arith_Shift   : in  std_logic;
      Shift         : in  std_logic_vector(0 to 5);
      Barrel_Result : out std_logic_vector(0 to C_DATA_SIZE-1));
  end component barrel_shift;

  component Result_Mux is
    generic (
      C_DATA_SIZE : natural range 4 to 64;
      C_TARGET    : TARGET_FAMILY_TYPE
      );
    port (
      Clk                : in  std_logic;
      Reset              : in  boolean;
      Result_Sel         : in  std_logic_vector(0 to 1);
      Doublet_Read       : in  boolean;
      Quadlet_Read       : in  boolean;
      -- Hexlet_Read        : in  boolean;
      Sext8              : in  boolean;
      Sext16             : in  boolean;
      -- Sext32             : in  boolean;
      PCMP_Instr         : in  boolean;
      Op1                : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Mul_Result         : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Other_Result       : in  std_logic_vector(0 to C_DATA_SIZE-1);
      ALU_Result         : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Shift_Logic_Result : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Data_Read          : in  std_logic_vector(0 to C_DATA_SIZE-1);
      EX_Result          : out std_logic_vector(0 to C_DATA_SIZE-1);
      New_Reg_Value      : out std_logic_vector(0 to C_DATA_SIZE-1)
      );
  end component Result_Mux;

  component Zero_Detect is
    generic (
      -- Size generics
      C_DATA_SIZE : natural range 4 to 64;
      C_TARGET    : TARGET_FAMILY_TYPE
      );
    port (
      -- Zero flag signals
      Reg_Test_Equal   : in  std_logic;
      Reg_Test_Equal_N : in  std_logic;
      EX_Result        : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Reg_Zero         : out std_logic);
  end component Zero_Detect;

  component MSR_Reg is
    generic (
      -- Size generics
      C_TARGET         : TARGET_FAMILY_TYPE;
      C_RESET_MSR      : MSR_TYPE;
      C_PVR            : integer := 0;
      C_USE_DIV        : boolean := false;
      C_USE_D_OPB      : boolean := false;
      C_FSL_LINKS      : integer := 0;
      C_USE_ICACHE     : boolean := false;
      C_USE_DCACHE     : boolean := false;
      C_DATA_SIZE      : natural := 32;
      C_USE_MSR_INSTR  : integer := 0;
      C_USE_EXCEPTIONS : boolean := false
      );
    port (
      Clk   : in std_logic;
      Reset : in boolean;

      Write_Carry        : in  boolean;
      New_Carry          : in  std_logic;
      MTS_Write          : in  boolean;
      Disable_Interrupts : in  boolean;
      Enable_Interrupts  : in  boolean;
      Set_BIP            : in  boolean;
      Reset_BIP          : in  boolean;
      Disable_Exceptions : in  boolean;
      Enable_Exceptions  : in  boolean;
      Set_EIP            : in  boolean;
      Reset_EIP          : in  boolean;
      FSL_Write_Carry    : in  std_logic;
      FSL_Carry          : in  std_logic;
      Div_By_Zero        : in  std_logic;
      Set_FSL_Error      : in  boolean;
      Op1                : in  std_logic_vector(C_DATA_SIZE-MSR_REG_TYPE'length to C_DATA_SIZE-1);
      Op2                : in  std_logic_vector(C_DATA_SIZE-MSR_REG_TYPE'length to C_DATA_SIZE-1);
      MSRxxx_Instr       : in  boolean;
      MSRclr_Instr       : in  boolean;
      MSR                : out MSR_REG_TYPE);
  end component MSR_Reg;

  component PC_Module is
    generic (
      -- Size generics
      C_DATA_SIZE     : natural range 4 to 64;
      C_TARGET        : TARGET_FAMILY_TYPE;
      C_PC_START_ADDR : string
      );
    port (
      Clk   : in std_logic;
      Reset : in boolean;

      Stop_Instr_Fetch : in std_logic;
      OF_PipeRun       : in boolean;

      PC_Incr    : in boolean;
      Jump       : in boolean;
      ALU_Result : in std_logic_vector(0 to C_DATA_SIZE-1);

      PC_Write    : in boolean;
      IReady      : in std_logic;
      Buffer_Addr : in std_logic_vector(0 to 3);

      PC_OF      : out std_logic_vector(0 to C_DATA_SIZE-1);
      PC_EX      : out std_logic_vector(0 to C_DATA_SIZE-1);
      Instr_Addr : out std_logic_vector(0 to C_DATA_SIZE-1));
  end component PC_Module;

  component Div_unit is
    generic (
      C_TARGET    : TARGET_FAMILY_TYPE;
      C_DATA_SIZE : natural range 8 to 64);
    port (
      Clk         : in  std_logic;
      Reset       : in  boolean;
      OF_PipeRun  : in  boolean;
      Start_Div   : in  std_logic;
      Not_Div_Op  : in  std_logic;