data_flow.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: data_flow.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Data_Flow - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        data_flow.vhd
-- Version:         v1.00a
-- Description:     MicroBlaze execution unit and registers      
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              data_flow.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--   BLT    2001-04-12    Added U_SET for grouping RLOCs
--   goran  2001-06-13    New value to MSR is coming directly from shift_logic
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Data_Flow is

  generic (

    -- global generics
    C_DATA_SIZE      : natural range 4 to 64 := 64;
    C_TARGET         : TARGET_FAMILY_TYPE;
    C_AREA_OPTIMIZED : integer               := 0;

    -- generics for "Operand_Select_I"
    C_PC_START_ADDR  : string  := "00000000";
    C_EXCEPTION_ADDR : string := "00000020";
    C_INTERRUPT_ADDR : string := "00000010";
    C_EXT_BRK_ADDR   : string := "00000018";

    C_USE_EXCEPTIONS : boolean := false;
    
    -- generics for using Barrel Shifter
    C_USE_BARREL : integer := 1;

    C_USE_DIV : integer := 1;

    -- generic for using the hardware multipliers
    C_USE_HW_MUL : boolean := true;
    C_USE_MUL64  : boolean := false;

    C_USE_FPU : integer := 0;

    -- Enable extra instructions like PCMP
    C_USE_PCMP_INSTR : boolean := true;

    C_USE_MSR_INSTR : integer := 0;

    C_BUFFER_SIZE   : natural range 1 to 16 := 8;

    C_DEBUG_ENABLED : integer               := 0;

    C_FSL_LINKS               : integer;
    C_USE_EXTENDED_FSL_INSTR  : integer := 0;
    C_MAX_FSL_LINKS           : natural;

    -- Generics used by PVR
    C_PVR                   : integer;   -- Which PVR mode None=0, Basic=1, Full=2
    C_MB_VERSION            : std_logic_vector(0 to 7);
    C_PVR_USER1             : std_logic_vector(0 to 7);
    C_PVR_USER2             : std_logic_vector(0 to 31);
    C_INTERCONNECT          : integer;
    C_D_OPB                 : integer;
    C_D_PLB                 : integer;
    C_D_LMB                 : integer;
    C_I_OPB                 : integer;
    C_I_PLB                 : integer;
    C_I_LMB                 : integer;
    C_INTERRUPT_IS_EDGE     : integer;
    C_EDGE_IS_POSITIVE      : integer;
    C_OPCODE_0x0_ILLEGAL    : integer;
    C_UNALIGNED_EXCEPTIONS  : integer;
    C_ILL_OPCODE_EXCEPTION  : integer;
    C_IOPB_BUS_EXCEPTION    : integer;
    C_DOPB_BUS_EXCEPTION    : integer;
    C_IPLB_BUS_EXCEPTION    : integer;
    C_DPLB_BUS_EXCEPTION    : integer;
    C_DIV_ZERO_EXCEPTION    : integer;
    C_FPU_EXCEPTION         : integer;
    C_FSL_EXCEPTION         : integer;
    C_NUMBER_OF_PC_BRK      : integer;
    C_NUMBER_OF_RD_ADDR_BRK : integer;
    C_NUMBER_OF_WR_ADDR_BRK : integer;
    C_USE_ICACHE            : integer;
    C_ADDR_TAG_BITS         : integer;
    C_ICACHE_USE_FSL        : integer;
    C_ALLOW_ICACHE_WR       : integer;
    C_ICACHE_LINE_LEN       : integer;
    C_CACHE_BYTE_SIZE       : integer;
    C_ICACHE_ALWAYS_USED    : integer;
    C_USE_DCACHE            : integer;
    C_DCACHE_ADDR_TAG       : integer;
    C_DCACHE_USE_FSL        : integer;
    C_ALLOW_DCACHE_WR       : integer;
    C_DCACHE_LINE_LEN       : integer;
    C_DCACHE_BYTE_SIZE      : integer;
    C_DCACHE_ALWAYS_USED    : integer;
    C_ICACHE_BASEADDR       : std_logic_vector(0 to 31);
    C_ICACHE_HIGHADDR       : std_logic_vector(0 to 31);
    C_DCACHE_BASEADDR       : std_logic_vector(0 to 31);
    C_DCACHE_HIGHADDR       : std_logic_vector(0 to 31);
    C_USE_MMU               : integer;
    C_MMU_DTLB_SIZE         : integer;
    C_MMU_ITLB_SIZE         : integer;
    C_MMU_TLB_ACCESS        : integer;
    C_MMU_ZONES             : integer;
    C_RESET_MSR             : MSR_TYPE
    );

  port (

    -- global ports
    Clk        : in std_logic;
    Reset      : in boolean;
    OF_PipeRun : in boolean;

    -- ports to "Register_File_I"
    Write_Addr : in  std_logic_vector(0 to 4);
    Reg1_Addr  : in  std_logic_vector(0 to 4);
    Reg2_Addr  : in  std_logic_vector(0 to 4);
    Reg_Write  : in  boolean;
    Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);

    -- ports to "Operand_Select_I"
    Imm_Value               : in  std_logic_vector(0 to 15);
    OpSel1_PC               : in  boolean;
    OpSel1_SPR              : in  boolean;
    -- OpSel1_FSR              : in  boolean;
    OpSel2_Imm              : in  boolean;
    Take_Ext_BRK            : in  boolean;
    Take_Exception          : in  boolean;
    Take_Interrupt          : in  boolean;
    Store_PC_For_Intr       : in  boolean;
    Store_PC_For_Intr_NoImm : in  boolean;
    Res_Forward1            : in  boolean;
    Res_Forward2            : in  boolean;
    Imm_Instr               : in  boolean;
    Use_Imm_Reg             : in  boolean;
    MFS_Reg_Sel             : in  std_logic_vector(0 to 2);
    BTR                     : in  BTR_TYPE;
    EAR                     : in  EAR_TYPE;
    EDR                     : in  EDR_TYPE;
    ESR                     : in  ESR_TYPE;
    word_r1_r2_unalignment  : out std_logic;
    word_r1_imm_unalignment : out std_logic;
    halfword_unalignment    : out std_logic;

    -- ports to "ALU_I"
    ALU_Op        : in  std_logic_vector(0 to 1);
    Compare_Instr : in  std_logic;
    Unsigned_Op   : in  std_logic;
    Carry_In      : in  std_logic;
    ALU_Carry     : out std_logic;
    Data_Addr     : out std_logic_vector(0 to C_DATA_SIZE-1);

    -- ports to "Shift_Logic_Module_I"
    Sext8           : in  boolean;
    Sext16          : in  boolean;
    -- Sext32          : in  boolean;
    PCMP_Instr      : in  boolean;
    Shift_Carry_In  : in  std_logic;
    Sign_Extend     : in  boolean;
    Shift_Oper      : in  std_logic_vector(0 to 1);
    Logic_Oper      : in  std_logic_vector(0 to 1);
    Select_Logic    : in  boolean;
    Shift_Carry_Out : out std_logic;

    -- ports to "Result_Mux_I"
    Result_Sel   : in std_logic_vector(0 to 1);
    Doublet_Read : in boolean;
    Quadlet_Read : in boolean;
    -- Hexlet_Read  : in boolean;
    Data_Read    : in std_logic_vector(0 to C_DATA_SIZE-1);

    -- ports to "Mul_Unit_I"
    EX_Not_Mul_Op   : in boolean;
    EX_Mulh_Instr   : in boolean;
    EX_Mulhu_Instr  : in boolean;
    EX_Mulhsu_Instr : in boolean;

    -- ports to "Barrel_Shifter_I"
    Arith_Shift   : in std_logic;
    Left_Shift    : in std_logic;
    Not_Barrel_Op : in std_logic;

    -- ports to "Zero_Detect_I"
    Reg_Test_Equal   : in  std_logic;
    Reg_Test_Equal_N : in  std_logic;
    Reg_zero         : out std_logic;
    Reg_neg          : out std_logic;

    -- ports to "MSR_Reg_I"
    Write_Carry        : in  boolean;
    New_Carry          : in  std_logic;
    MTSMSR_Write       : in  boolean;
    Disable_Interrupts : in  boolean;
    Enable_Interrupts  : in  boolean;
    Set_BIP            : in  boolean;
    Reset_BIP          : in  boolean;
    BIP_Active         : out boolean;
    Carry              : out std_logic;
    Enable_Interrupt   : out boolean;
    Enable_BusLock     : out boolean;
    MSRxxx_Instr       : in  boolean;
    MSRclr_Instr       : in  boolean;

    Disable_Exceptions : in  boolean;
    Enable_Exceptions  : in  boolean;
    Exceptions_Enabled : out boolean;
    Set_EIP            : in  boolean;
    Reset_EIP          : in  boolean;
    EIP_Active         : out boolean;

    -- ports to "PC_Module_I"
    PC_Incr     : in  boolean;
    Jump        : in  boolean;
    PC_Write    : in  boolean;
    IReady      : in  std_logic;
    Buffer_Addr : in  std_logic_vector(0 to 3);
    Instr_Addr  : out std_logic_vector(0 to C_DATA_SIZE-1);

    Op1_Low : out std_logic_vector(0 to 1);
    Op2_Low : out std_logic_vector(0 to 1);

    -- Debug Signals
    Stop_Instr_Fetch : in  std_logic;
    Dbg_Inhibit_EX   : in  std_logic;
    Op1              : out std_logic_vector(0 to C_DATA_SIZE-1);
    PC_OF            : out std_logic_vector(0 to C_DATA_SIZE-1);
    
    -- Operand 2
    Op2              : out std_logic_vector(0 to C_DATA_SIZE-1);

    -- PVR signals
    MEM_PVR_Select  : in std_logic_vector(0 to 3);
    MEM_Sel_SPR_PVR : in boolean;

    -- Trace signals
    PC_EX         : out std_logic_vector(0 to C_DATA_SIZE-1);
    MSR           : out MSR_REG_TYPE;
    New_Reg_Value : out std_logic_vector(0 to C_DATA_SIZE-1);

    -- FSL Links signal
    FSL_Get_No            : out natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
    FSL_Get_Data          : in  std_logic_vector(0 to C_DATA_SIZE-1);  -- Data that is received
    EX_FSL_Control_Error  : in  std_logic;  -- A FSL Get control bit mismatch has occured
    FSL_Put_No            : out natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
    FSL_Put_Data          : out std_logic_vector(0 to C_DATA_SIZE-1);  -- Data that is received
    EX_FSL_Write_Carry    : in  std_logic;
    EX_FSL_Carry          : in  std_logic;

    -- Div Unit signals
    Start_Div   : in  std_logic;
    Not_Div_Op  : in  std_logic;
    Div_Done    : out std_logic;
    Div_By_Zero : out std_logic;

    -- FPU signals
    FPU_Op         : in  std_logic_vector(0 to 2);
    FPU_Cond       : in  std_logic_vector(0 to 2);
    Start_FPU      : in  std_logic;
    Not_FPU_Op     : in  std_logic;
    FSR_Write      : in boolean;
    FPU_Done       : out std_logic;
    FPU_Excep      : out std_logic;
    
    -- Instruction Cache signal
    ICache_Enabled : out boolean;
    DCache_Enabled : out boolean
    );

end entity Data_Flow;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of Data_Flow is

  -----------------------------------------------------------------------------
  -- Constant declarations
  -----------------------------------------------------------------------------
  
  constant FSL_EXCEPTION_ON  : boolean := ( C_FSL_LINKS > 0 ) and (C_FSL_EXCEPTION /= 0) and (C_USE_EXTENDED_FSL_INSTR /= 0);
  
  -----------------------------------------------------------------------------
  -- Internal signal declarations
  -----------------------------------------------------------------------------

  -- outputs of "Register_File_I"
  signal reg1_Data    : std_logic_vector(0 to C_DATA_SIZE-1);
  signal reg2_Data    : std_logic_vector(0 to C_DATA_SIZE-1);
  signal write_addr_I : std_logic_vector(0 to 4);
  signal reg_write_I  : rboolean; -- resolved boolean

  -- outputs of "Operand_Select_I"
  signal reg1  : std_logic_vector(0 to C_DATA_SIZE-1);
  signal op1_i : std_logic_vector(0 to C_DATA_SIZE-1);
  signal op2_i : std_logic_vector(0 to C_DATA_SIZE-1);
  signal op2_C : std_logic_vector(0 to C_DATA_SIZE-1);
  signal Set_FSL_Error : boolean;
  signal FSL_No: natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
  

  -- outputs of "ALU_I"