dopb_interface.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: dopb_interface.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- DOPB_Interface - entity/architecture
-------------------------------------------------------------------------------
--
-- ****************************************************************************
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-- **
-- ** Unmodified source code is guaranteed to place and route,
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--
-------------------------------------------------------------------------------
-- Filename:        dopb_interface.vhd
-- Version:         v1.00a
-- Description:     Data side OPB interface for MicroBlaze
--
-------------------------------------------------------------------------------
-- Structure: 
--              dopb_interface.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity DOPB_Interface is
  generic (
    C_OPB_WIDTH           : natural := 32;
    C_DELAYED_DATA_STROBE : boolean := false
    );
  port (
    -- global signals
    Clk   : in std_logic;
    Reset : in std_logic;

    -- OPB signals
    DM_ABus      : out std_logic_vector(0 to C_OPB_WIDTH-1);
    DM_BE        : out std_logic_vector(0 to (C_OPB_WIDTH-1)/8);
    DM_busLock   : out std_logic;
    DM_DBus      : out std_logic_vector(0 to C_OPB_WIDTH-1);
    DM_request   : out std_logic;
    DM_RNW       : out std_logic;
    DM_select    : out std_logic;
    DM_seqAddr   : out std_logic;
    DOPB_DBus    : in  std_logic_vector(0 to C_OPB_WIDTH-1);
    DOPB_errAck  : in  std_logic;
    DOPB_MGrant  : in  std_logic;
    DOPB_retry   : in  std_logic;
    DOPB_timeout : in  std_logic;
    DOPB_xferAck : in  std_logic;

    -- Local Bus signals
    MEM_DataBus_Access      : in std_logic;
    MEM_DataBus_Addr        : in DATA_TYPE;
    MEM_DataBus_Write       : in std_logic;
    MEM_DataBus_Write_Data  : in DATA_TYPE;
    MEM_DataBus_Byte_Enable : in DATA_BE_TYPE;
    MEM_DataBus_Read        : in std_logic;

    WB_DOPB_Data_Strobe : out std_logic;
    WB_DOPB_Read_Data   : out DATA_TYPE;

    -- other signals
    MEM_DataBus_Drop_Request   : in  std_logic;
    MEM_DataBus_Enable_BusLock : in  std_logic;
    MEM_DOPB_Data_Strobe       : out std_logic;
    MEM_DOPB_Exception         : out std_logic
    );

end entity DOPB_Interface;

architecture IMP of DOPB_Interface is

  signal valid_retry    : std_logic;
  signal valid_retry_d1 : std_logic;
  signal valid_timeout  : std_logic;
  signal valid_errAck   : std_logic;
  signal valid_xferAck  : std_logic;

  signal valid_acknowledge    : std_logic;
  signal terminate_access     : std_logic;
  signal access_error         : std_logic;
  signal dM_request_i         : std_logic;
  signal dM_select_i          : std_logic;
  signal request_granted      : std_logic;
  signal mem_access_completed : std_logic;

  signal inhibit_further_requests : std_logic;
  signal bus_access_ended         : std_logic;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
  -----------------------------------------------------------------------------
  -- Unused signals
  -----------------------------------------------------------------------------
  -- sequentioal addressing not used by MicroBlaze
  DM_seqAddr <= '0';

  -----------------------------------------------------------------------------
  -- Qualify handshake signals valid for this master
  -----------------------------------------------------------------------------
  valid_retry   <= dM_select_i and DOPB_retry;
  valid_timeout <= dM_select_i and DOPB_timeout;
  valid_xferAck <= dM_select_i and DOPB_xferAck;
  valid_errAck  <= dM_select_i and DOPB_errAck;

  -----------------------------------------------------------------------------
  -- Arbitration signalling
  -----------------------------------------------------------------------------
  dm_request_i <= MEM_DataBus_Access and
                  not MEM_DataBus_Drop_Request and  -- remove request if XCL or LMB acks 
                  not dM_select_i and   -- remove request once granted
                  not valid_retry_d1 and  -- lower request one cycle after retry
                  not inhibit_further_requests;  -- Inhibit a new request at the
                                              -- end of an existing cycle

  DM_request <= dm_request_i;

  valid_acknowledge <= valid_xferAck or valid_retry;
  terminate_access  <= valid_acknowledge or valid_timeout or valid_errAck;

  -- on single slave busses MGrant is always high
  -- must limit singalling to actual requests
  request_granted <= DOPB_MGrant and dm_request_i;

  DM_Select <= dM_select_i;

  address_data_DFF : process (Clk) is
  begin  -- process data_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (reset = '1') or (terminate_access = '1') then
        DM_ABus     <= (others => '0');
        DM_RNW      <= '0';
        dM_select_i <= '0';
        DM_DBus     <= (others => '0');
        DM_BE       <= (others => '0');
      else
        if request_granted = '1' then
          DM_ABus     <= MEM_DataBus_Addr;
          DM_RNW      <= MEM_DataBus_Read;
          dM_select_i <= '1';
          if (MEM_DataBus_Write = '1') then
            DM_DBus <= MEM_DataBus_Write_Data;
          end if;
          DM_BE <= MEM_DataBus_Byte_Enable;
        end if;
      end if;
    end if;
  end process address_data_DFF;

  -----------------------------------------------------------------------------
  -- DM_buslock set to '1' on next Grant. Grant not generated during lock so
  -- clear must be done as soon as happens
  -----------------------------------------------------------------------------
  BusLock_DFF : process (Clk) is
  begin
    if Clk'event and Clk = '1' then
      if Reset = '1' then
        DM_busLock <= '0';
      else
        if MEM_DataBus_Enable_BusLock = '0' or valid_retry = '1' then
          DM_busLock <= '0';
        elsif request_granted = '1'then
          DM_busLock <= MEM_DataBus_Enable_BusLock;
        end if;
      end if;
    end if;
  end process BusLock_DFF;

  -----------------------------------------------------------------------------
  -- Data OPB access completion
  -----------------------------------------------------------------------------
  access_error <= valid_errAck or (valid_timeout and not valid_acknowledge);

  MEM_DOPB_Data_Strobe <= bus_access_ended;

  access_completion_DFF : process (Clk)
  begin
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then
        WB_DOPB_Data_Strobe  <= '0';
        WB_DOPB_Read_Data    <= (others => '0');
        MEM_DOPB_Exception   <= '0';
        valid_retry_d1       <= '0';
        mem_access_completed <= '0';
      else
        valid_retry_d1       <= valid_retry;
        mem_access_completed <= valid_xferAck or access_error;
        WB_DOPB_Data_Strobe  <= bus_access_ended;
        MEM_DOPB_Exception   <= access_error;
        if valid_xferAck = '1' or
          access_error = '1' then  -- create same read_data behavior as in v400a
          WB_DOPB_Read_Data <= DOPB_DBus;
        end if;
      end if;
    end if;
  end process access_completion_DFF;

  -----------------------------------------------------------------------------
  -- Delaying Data_strobe one clock cycle compared to the exception signal
  -- This is used by the area version when DataBus exception is implemented to
  -- be able to get time to generate an exception without the pipe is moving
  -----------------------------------------------------------------------------
  Delaying_Data_strobe : if (C_DELAYED_DATA_STROBE) generate
    Delay_Strobe : process (Clk) is
    begin  -- process Delay_Strobe
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset = '1' then             -- synchronous reset (active high)
          bus_access_ended      <= '0';
        else
          bus_access_ended      <= mem_access_completed;
        end if;
      end if;
    end process Delay_Strobe;
    inhibit_further_requests <= mem_access_completed or bus_access_ended;
  end generate Delaying_Data_strobe;

  No_Delaying_of_Data_Strobe: if (not C_DELAYED_DATA_STROBE) generate
    bus_access_ended         <= mem_access_completed;
    inhibit_further_requests <= mem_access_completed;
  end generate No_Delaying_of_Data_Strobe;

end architecture IMP;