debug.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  end process Command_Reg_DFF;

  Reg_access_Delay : process (Clk) is
  begin  -- process Reg_access_Delay
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then
        read_register_PC_1  <= '0';
        read_register_MSR_1 <= '0';
      else
        read_register_PC_1  <= read_register_PC;
        read_register_MSR_1 <= read_register_MSR;
      end if;
    end if;
  end process Reg_access_Delay;

  -----------------------------------------------------------------------------
  -- Do the TDO output mux
  -----------------------------------------------------------------------------
  TDO_Mux : process (TDO_Status_Reg, Status_Reg_En, TDO_Data_Reg, Data_Read_Reg_En, Config_Reg_En, TDO_Config_Word) is
  begin  -- process TDO_Mux
    if (Status_Reg_En = '1') then
      TDO <= TDO_Status_Reg;
    elsif (Data_Read_Reg_En = '1') then
      TDO <= TDO_Data_Reg;
    elsif (Config_Reg_En = '1') then      
      TDO <= TDO_Config_Word;
    else
      TDO <= '0';
    end if;
  end process TDO_Mux;

  -----------------------------------------------------------------------------
  -- Instanciate all PC breakpoints
  -----------------------------------------------------------------------------

  Enable_PC_Brks : process (Reg_En) is
  begin  -- process Enable_PC_Brks
    which_pc <= (others => '0');        --default
    if (Reg_En(0) = '1') then
      for I in 0 to C_Nr_of_Brks-1 loop
        if (I = to_integer(unsigned(Reg_En(1 to 4)))) then
          which_pc(I) <= '1';
        end if;
      end loop;  -- I
    end if;
  end process Enable_PC_Brks;

  Using_PC_Breakpoints : if (C_NUMBER_OF_PC_BRK > 0) generate
    
    All_PC_Brks : for I in 0 to C_NUMBER_OF_PC_BRK-1 generate

      address_hit_I : address_hit
        generic map (
          C_TARGET => C_TARGET,
          C_FIRST  => (I = 0),
          No_Bits  => C_DATA_SIZE)      -- [natural]
        port map (
          Address       => PC_OF,     -- [in  std_logic_vector(0 to No_Bits-1)]
          Armed         => armed,       -- [in  std_logic]
          TClk          => TClk,        -- [in  std_logic]
          TDI           => TDI,         -- [in  std_logic]
          SRL16_En      => which_pc(I),  -- [in  std_logic]
          Single_Step_N => single_Step_N,  -- [in  std_logic]
          Hit           => pc_hit_i(I));   -- [out std_logic]
    end generate All_PC_Brks;
    
  end generate Using_PC_Breakpoints;

  -----------------------------------------------------------------------------
  -- Insert logic for stopping and single-stepping
  -----------------------------------------------------------------------------
  No_PC_Breakpoints : if (C_NUMBER_OF_PC_BRK = 0) generate
    pc_hit_i(C_NUMBER_OF_RD_ADDR_BRK + C_NUMBER_OF_WR_ADDR_BRK) <= not single_Step_N;
  end generate No_PC_Breakpoints;

  -----------------------------------------------------------------------------
  -- Insert all Read Address Watchpoints
  -----------------------------------------------------------------------------
  Using_Rd_Addr_Breakpoints : if (C_NUMBER_OF_RD_ADDR_BRK > 0) generate

    read_instr_i <= Read_Instr and DReady;

    All_Rd_Addr_Breakpoints : for I in 0 to C_NUMBER_OF_RD_ADDR_BRK - 1 generate
      signal data_addr_delayed  : std_logic_vector(0 to 31);
      signal read_instr_delayed : std_logic;
    begin

      -------------------------------------------------------------------------
      -- The signals to the address hit must be aligned to the same cycle
      -- Since New_Reg_Value is one clock cycle delayed, the signals data_addr
      -- and read_instr_i must also be delayed one clock cycle
      -------------------------------------------------------------------------
      Sync_Up_Data : process (Clk) is
      begin  -- process Sync_Up_Data
        if Clk'event and Clk = '1' then  -- rising clock edge
          if Reset then                  -- synchronous reset (active high)
            data_addr_delayed  <= (others => '0');
            read_instr_delayed <= '0';
          else
            data_addr_delayed  <= data_addr;
            read_instr_delayed <= read_instr_i;
          end if;
        end if;
      end process Sync_Up_Data;
      
      address_data_hit_rd : address_data_hit
        generic map (
          C_TARGET => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          No_Bits  => C_DATA_SIZE)      -- [natural]
        port map (
          Address  => data_addr_delayed,  -- [in  std_logic_vector(0 to No_Bits-1)]
          Data     => New_Reg_Value,  -- [in  std_logic_vector(0 to No_Bits-1)]
          Armed    => read_instr_delayed,               -- [in  std_logic]
          TClk     => TClk,             -- [in  std_logic]
          TDI      => TDI,              -- [in  std_logic]
          SRL16_En => which_pc(I+C_NUMBER_OF_PC_BRK),   -- [in  std_logic]
          Hit      => pc_hit_i(I+C_NUMBER_OF_PC_BRK));  -- [out std_logic]

    end generate All_Rd_Addr_Breakpoints;

  end generate Using_Rd_Addr_Breakpoints;

  Using_Wr_Addr_Breakpoints : if (C_NUMBER_OF_WR_ADDR_BRK > 0) generate

    All_Wr_Addr_Breakpoints : for I in 0 to C_NUMBER_OF_WR_ADDR_BRK - 1 generate
      address_data_hit_1 : address_data_hit
        generic map (
          C_TARGET => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          No_Bits  => C_DATA_SIZE)      -- [natural]
        port map (
          Address  => Data_Addr,      -- [in  std_logic_vector(0 to No_Bits-1)]
          Data     => Data_Write,     -- [in  std_logic_vector(0 to No_Bits-1)]
          Armed    => Write_Instr,      -- [in  std_logic]
          TClk     => TClk,             -- [in  std_logic]
          TDI      => TDI,              -- [in  std_logic]
          SRL16_En => which_pc(I+C_NUMBER_OF_PC_BRK + C_NUMBER_OF_RD_ADDR_BRK),  -- [in  std_logic_vector(0 to ((No_Bits+3)/4)-1)]
          Hit      => pc_hit_i(I + C_NUMBER_OF_PC_BRK + C_NUMBER_OF_RD_ADDR_BRK)  -- [out std_logic]
          );
    end generate All_Wr_Addr_Breakpoints;
  end generate Using_Wr_Addr_Breakpoints;

  Fixing_PC_Brk : process (pc_hit_i) is
    variable pc_brk_i    : std_logic;
    variable watch_brk_i : std_logic;
  begin  -- process Fixing_PC_Brk
    pc_brk_i := '0';
    for I in 0 to C_NR_OF_BRKS - 1 loop
      pc_brk_i := pc_brk_i or pc_hit_i(I);
    end loop;  -- I
    pc_brk <= pc_brk_i;
    if (C_NUMBER_OF_RD_ADDR_BRK + C_NUMBER_OF_WR_ADDR_BRK > 0) then 
      watch_brk_i := '0';
      for I in C_NUMBER_OF_PC_BRK to C_NUMBER_OF_PC_BRK +
                                     C_NUMBER_OF_RD_ADDR_BRK +
                                     C_NUMBER_OF_WR_ADDR_BRK - 1 loop 
        watch_brk_i := watch_brk_i or pc_hit_i(I);       
      end loop;
      watchpoint_hit <= watch_brk_i;
    else
      watchpoint_hit <= '0';
    end if;
  end process Fixing_PC_Brk;

  point_hit     <= pc_brk or watchpoint_hit_hold;
  pc_brk_insert <= point_hit or New_Dbg_Instr2_CLK;

  --------------------------------------------------------------------------------------------------
  -- Need to hold watchpoint hits since the access can finish before next instruction is ready for execution
  --------------------------------------------------------------------------------------------------
  Hold_Watchpoints_Hits: process (Clk) is
  begin  -- process Hold_Watchpoints_Hits
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset then               -- synchronous reset (active high)
        watchpoint_hit_hold <= '0';         
      else
        if (OF_PipeRun) then
          watchpoint_hit_hold <= '0';
        elsif (watchpoint_hit = '1') then
          watchpoint_hit_hold <= '1';
        end if;
      end if;
    end if;
  end process Hold_Watchpoints_Hits;

  
  Locking_PC_Hit : process (Clk) is
  begin  -- process Locking_PC_Hit
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then
        pc_hit <= (others => '0');
      else
        if (pc_brk = '1') then
          pc_hit <= (others => '0');
          for I in 0 to C_NR_OF_BRKS - 1 loop
            pc_hit(I) <= pc_hit_i(I);
          end loop;
        end if;
      end if;
    end if;
  end process Locking_PC_Hit;

  -----------------------------------------------------------------------------
  -- Need to stop the CPU when a Breakpoint is reached
  -----------------------------------------------------------------------------

  single_Step_CPU   <= free_running or start_single_step or continue_from_brk when not reset else '1';
  single_Step_CPU_1 <= single_Step_CPU or Start_Dbg_Exec;
  single_Step_CPU_2 <= single_Step_CPU or Instr_Insert_Reg_En_Clk;

  Dbg_Stop_DFF : process (Clk) is
    variable Want_to_Stop : std_logic;
  begin  -- process Dbg_Stop_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if Reset then
        dbg_Stop_i   <= '0';
        Want_to_Stop := '0';
      else
        if (Stop_CPU_i = '1') then
          dbg_Stop_i   <= '0';
          Want_to_Stop := '0';
        elsif (Dbg_Stop = '1') then
          if (Ok_To_Stop = '1') then
            dbg_Stop_i <= '1';
          else
            Want_to_Stop := '1';
          end if;
        elsif (Want_to_Stop = '1') then
          dbg_Stop_i <= Ok_To_Stop;
        end if;
      end if;
    end if;
  end process Dbg_Stop_DFF;

  Using_FPGA : if (C_TARGET /= RTL) generate
    Stop_CPU_FDRSE : FDRSE
      port map (
        Q  => stop_CPU_i,               -- [out std_logic]
        C  => Clk,                      -- [in  std_logic]
        CE => Ok_To_Stop,               -- [in  std_logic]
        D  => point_hit,                   -- [in  std_logic]
        R  => single_Step_CPU_2,        -- [in  std_logic]
        S  => dbg_Stop_i);              -- [in std_logic]

    Dbg_Inhibit_EX_FDRSE : FDRSE
      port map (
        Q  => Dbg_Inhibit_EX_i,         -- [out std_logic]
        C  => Clk,                      -- [in  std_logic]
        CE => Ok_To_Stop,               -- [in  std_logic]
        D  => point_hit,                   -- [in  std_logic]
        R  => single_Step_CPU_1,        -- [in  std_logic]
        S  => dbg_Stop_i);              -- [in std_logic]

    
    Stop_Instr_Fetch_FDRSE : FDRSE
      port map (
        Q  => Stop_Instr_Fetch_i,       -- [out std_logic]
        C  => Clk,                      -- [in  std_logic]
        CE => Ok_To_Stop,               -- [in  std_logic]
        D  => pc_brk_insert,            -- [in  std_logic]
        R  => single_Step_CPU,          -- [in  std_logic]
        S  => dbg_Stop_i);              -- [in std_logic]

  end generate Using_FPGA;

  Stop_Instr_Fetch <= Stop_Instr_Fetch_i;

  Using_RTL : if (C_TARGET = RTL) generate

    Stop_CPU_DFF : process (Clk) is
    begin  -- process Stop_CPU_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if single_Step_CPU = '1' then   -- synchronous reset (active high)
          stop_CPU_i <= '0';
        elsif (dbg_stop_i = '1') then
          stop_CPU_i <= '1';
        elsif (Ok_To_Stop = '1') then
          stop_CPU_i <= point_hit;
        end if;
      end if;
    end process Stop_CPU_DFF;

    Dbg_Inhibit_EX_DFF : process (Clk) is
    begin  -- process Dbg_Inhibit_EX_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if single_Step_CPU = '1' then   -- synchronous reset (active high)
          Dbg_Inhibit_EX_i <= '0';
        elsif (dbg_stop_i = '1') then
          Dbg_Inhibit_EX_i <= '1';
        elsif (Ok_To_Stop = '1') then
          Dbg_Inhibit_EX_i <= point_hit;
        end if;
      end if;
    end process Dbg_Inhibit_EX_DFF;

    Stop_Instr_Fetch_DFF : process (Clk) is
    begin  -- process Stop_Instr_Fetch_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if single_Step_CPU = '1' then   -- synchronous reset (active high)
          Stop_Instr_Fetch_i <= '0';
        elsif (dbg_stop_i = '1') then
          Stop_Instr_Fetch_i <= '1';
        elsif (Ok_To_Stop = '1') then
          Stop_Instr_Fetch_i <= pc_brk_insert;
        end if;
      end if;
    end process Stop_Instr_Fetch_DFF;

  end generate Using_RTL;

  stop_CPU <= stop_CPU_i;

  Dbg_Inhibit_EX <= Dbg_Inhibit_EX_i;
  
end architecture IMP;