debug.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  signal start_single_cmd  : std_logic;
  signal start_single_step : std_logic;
  signal continue_from_brk : std_logic;
  signal single_Step_N     : std_logic;
  signal single_Step_CPU   : std_logic;
  signal single_Step_CPU_1 : std_logic;
  signal single_Step_CPU_2 : std_logic;

  signal single_step_count : std_logic_vector(0 to 1);

  signal status_reg : std_logic_vector(0 to 22) := (others => '0');
  -- Bit 0-15 BRK Hit
  -- Bit 16 Stopped
  -- Bit 17 Reset
  -- Bit 18 Instruction after a IMM instruction
  -- Bit 19 Delay_slot instruction
  -- Bit 20 Two instruction backwards was an IMM instruction
  -- Bit 21 MicroBlaze stalled due to FSL
  -- Bit 22 MicroBlaze stalled due to non responsive memory request

  signal Use_Imm_Reg_1      : boolean;
  signal Full_32_bit        : std_logic;
  signal Full_32_bit_1      : std_logic;
  signal delay_slot_instr_i : std_logic;

  signal fsl_stalled_1    : std_logic;
  signal memory_stalled_1 : std_logic;

  signal Command_Reg_Rst : std_logic;
  signal command_reg : std_logic_vector(0 to 1) := "00";
  -- Bit 0 Read Register MSR
  -- Bit 1 Read Register PC

  signal read_register_PC    : std_logic;
  signal read_register_PC_1  : std_logic;
  signal read_register_MSR   : std_logic;
  signal read_register_MSR_1 : std_logic;

  signal shift_datain  : std_logic_vector(0 to 31) := (others => '0');

  -- signal data_write_reg : std_logic_vector(0 to C_DATA_SIZE-1) := (others => '0');
  signal data_read_reg     : std_logic_vector(0 to C_DATA_SIZE) := (others => '0');
  signal data_rd_reg       : std_logic_vector(0 to C_DATA_SIZE);
  signal New_Instr_Reg_TCK : std_logic_vector(0 to C_DATA_SIZE-1);

  signal New_Dbg_Instr_TCK  : std_logic := '0';
  signal New_Dbg_Instr2_TCK : std_logic := '0';

  signal New_Dbg_Instr_CLK  : std_logic := '0';
  signal New_Dbg_Instr2_CLK : std_logic := '0';

  signal Debug_Ready_i  : std_logic;
  signal Start_Dbg_Exec : std_logic;

  signal pc_brk        : std_logic;
  signal pc_brk_insert : std_logic;
  signal stop_CPU_i    : std_logic;
  signal dbg_stop_i    : std_logic;

  signal point_hit           : std_logic;
  signal watchpoint_hit      : std_logic;
  signal watchpoint_hit_hold : std_logic;

  signal Stop_Instr_Fetch_i : std_logic;

  signal read_instr_i : std_logic;

  signal which_pc : std_logic_vector(0 to C_Nr_of_Brks-1);
  signal armed    : std_logic;
  signal pc_hit   : std_logic_vector(0 to 15);
  signal pc_hit_i : std_logic_vector(0 to C_Nr_of_Brks-1);

  signal shift_Count : std_logic_vector(7 downto 0) := (others => '0');

  signal read_pc : std_logic;

  signal Dbg_Inhibit_EX_i : std_logic;

  attribute INIT : string;
  
begin  -- architecture IMP

  -- Keep a counter on the number of bits in the data phase after a sync has
  -- been detected (only needed for BreakPoints and config register)
  Shift_Counter : process (TCLK) is
  begin  -- process Shift_Counter
    if TCLK'event and TCLK = '1' then   -- rising clock edge
      if (Shift = '1') then
        shift_Count <= std_logic_vector(unsigned(Shift_Count) + 1);
      else
        shift_Count <= (others => '0');
      end if;
    end if;
  end process Shift_Counter;

  Control_Reg_En      <= '1' when Reg_En(0 to 4) = "00001" else '0';
  Command_Reg_En      <= '1' when Reg_En(0 to 4) = "00010" else '0';
  Status_Reg_En       <= '1' when Reg_En(0 to 4) = "00011" else '0';
  Instr_Insert_Reg_En <= '1' when Reg_En(0 to 4) = "00100" else '0';
  Data_Read_Reg_En    <= '1' when Reg_En(0 to 4) = "00110" else '0';
  Config_Reg_En       <= '1' when Reg_En(0 to 4) = "00111" else '0';

  MB_Is_Stopped : process (Clk) is
  begin  -- process MB_Is_Stopped
    if Clk'event and Clk = '1' then     -- rising clock edge
      MB_Halted <= Stop_Instr_Fetch_i;
    end if;
  end process MB_Is_Stopped;
  -----------------------------------------------------------------------------
  -- Config Register handling
  -----------------------------------------------------------------------------
  Use_SRL16 : if (C_TARGET /= RTL) generate
    attribute INIT of SRL16E_1 : label is itohex(to_integer(unsigned(Config_Init_Word)), 4);
    attribute INIT of SRL16E_2 : label is itohex(to_integer(unsigned(Config_Init_Word2)), 4);
    signal tdo_config_word1    : std_logic_vector(0 to 13) := (others => '0');
  begin
    SRL16E_1 : SRL16E
      generic map (
        INIT => to_bitvector(Config_Init_Word)
      )
      port map (
        CE  => '0',                     -- [in  std_logic]
        D   => '0',                     -- [in  std_logic]
        Clk => TCLK,                    -- [in  std_logic]
        A0  => shift_Count(0),          -- [in  std_logic]
        A1  => shift_Count(1),          -- [in  std_logic]
        A2  => shift_Count(2),          -- [in  std_logic]
        A3  => shift_Count(3),          -- [in  std_logic]
        Q   => tdo_config_word1(0));    -- [out std_logic]

    SRL16E_2 : SRL16E
      generic map (
        INIT => to_bitvector(Config_Init_Word2)
      )
      port map (
        CE  => '0',                     -- [in  std_logic]
        D   => '0',                     -- [in  std_logic]
        Clk => TCLK,                    -- [in  std_logic]
        A0  => shift_Count(0),          -- [in  std_logic]
        A1  => shift_Count(1),          -- [in  std_logic]
        A2  => shift_Count(2),          -- [in  std_logic]
        A3  => shift_Count(3),          -- [in  std_logic]
        Q   => tdo_config_word1(1));    -- [out std_logic]

    The_Cache_Addresses : for I in 1 to 8 generate
      attribute INIT of SRL16E_Cache_I : label is itohex(to_integer(unsigned(Cache_Init_Word(I*16-1 downto (I-1)*16))), 4);
    begin
      SRL16E_Cache_I : SRL16E
        generic map (
          INIT => to_bitvector(Cache_Init_Word(I*16-1 downto (I-1)*16))
        )
        port map (
          CE  => '0',                   -- [in  std_logic]
          D   => '0',                   -- [in  std_logic]
          Clk => TCLK,                  -- [in  std_logic]
          A0  => shift_Count(0),        -- [in  std_logic]
          A1  => shift_Count(1),        -- [in  std_logic]
          A2  => shift_Count(2),        -- [in  std_logic]
          A3  => shift_Count(3),        -- [in  std_logic]
          Q   => tdo_config_word1(1+I));  -- [out std_logic]
    end generate The_Cache_Addresses;

    -- placed after cache information for compatibility with 8.1 tools
    SRL16E_3 : SRL16E
      generic map (
        INIT => to_bitvector(Config_Init_Word3)
        )
      port map (
        CE  => '0',                     -- [in  std_logic]
        D   => '0',                     -- [in  std_logic]
        Clk => TCLK,                    -- [in  std_logic]
        A0  => shift_Count(0),          -- [in  std_logic]
        A1  => shift_Count(1),          -- [in  std_logic]
        A2  => shift_Count(2),          -- [in  std_logic]
        A3  => shift_Count(3),          -- [in  std_logic]
        Q   => tdo_config_word1(10));   -- [out std_logic]

    -- PVR0 register information
    SRL16E_4 : SRL16E
      generic map (
        INIT => to_bitvector(Config_Init_Word4)
        )
      port map (
        CE  => '0',                     -- [in  std_logic]
        D   => '0',                     -- [in  std_logic]
        Clk => TCLK,                    -- [in  std_logic]
        A0  => shift_Count(0),          -- [in  std_logic]
        A1  => shift_Count(1),          -- [in  std_logic]
        A2  => shift_Count(2),          -- [in  std_logic]
        A3  => shift_Count(3),          -- [in  std_logic]
        Q   => tdo_config_word1(11));   -- [out std_logic]

    -- PVR1 register information
    Use_PVR_Full: if C_PVR = 2 generate
      -- High USER2 half-word
      SRL16E_5 : SRL16E
        generic map (
          INIT => to_bitvector(Config_Init_Word5)
          )
        port map (
          CE  => '0',                     -- [in  std_logic]
          D   => '0',                     -- [in  std_logic]
          Clk => TCLK,                    -- [in  std_logic]
          A0  => shift_Count(0),          -- [in  std_logic]
          A1  => shift_Count(1),          -- [in  std_logic]
          A2  => shift_Count(2),          -- [in  std_logic]
          A3  => shift_Count(3),          -- [in  std_logic]
          Q   => tdo_config_word1(12));   -- [out std_logic]
      -- Low USER2 half-word
      SRL16E_6 : SRL16E
        generic map (
          INIT => to_bitvector(Config_Init_Word6)
          )
        port map (
          CE  => '0',                     -- [in  std_logic]
          D   => '0',                     -- [in  std_logic]
          Clk => TCLK,                    -- [in  std_logic]
          A0  => shift_Count(0),          -- [in  std_logic]
          A1  => shift_Count(1),          -- [in  std_logic]
          A2  => shift_Count(2),          -- [in  std_logic]
          A3  => shift_Count(3),          -- [in  std_logic]
          Q   => tdo_config_word1(13));   -- [out std_logic]
    end generate Use_PVR_Full;

    SRL16_Mux : process (shift_Count, tdo_config_word1) is
    begin  -- process SRL16_Mux
      case shift_Count(7 downto 4) is
        when "0000" => TDO_Config_Word <= tdo_config_word1(0);
        when "0001" => TDO_Config_Word <= tdo_config_word1(1);
        when "0010" => TDO_Config_Word <= tdo_config_word1(2);
        when "0011" => TDO_Config_Word <= tdo_config_word1(3);
        when "0100" => TDO_Config_Word <= tdo_config_word1(4);
        when "0101" => TDO_Config_Word <= tdo_config_word1(5);
        when "0110" => TDO_Config_Word <= tdo_config_word1(6);
        when "0111" => TDO_Config_Word <= tdo_config_word1(7);
        when "1000" => TDO_Config_Word <= tdo_config_word1(8);
        when "1001" => TDO_Config_Word <= tdo_config_word1(9);
        when "1010" => TDO_Config_Word <= tdo_config_word1(10);
        when "1011" => TDO_Config_Word <= tdo_config_word1(11);
        when "1100" => TDO_Config_Word <= tdo_config_word1(12);
        when "1101" => TDO_Config_Word <= tdo_config_word1(13);
        when others => TDO_Config_Word <= tdo_config_word1(0);
      end case;
    end process SRL16_Mux;
  end generate Use_SRL16;

  Not_Use_SRL16 : if (C_TARGET = RTL) generate
    Config_TDO_Selecting: process (shift_Count) is
    begin  -- process Config_TDO_Selecting
      if (shift_Count(7 downto 4) = "0000") then
        TDO_Config_Word <= Config_Init_Word(to_integer(unsigned(shift_Count(3 downto 0))));
      elsif (shift_Count(7 downto 4) = "0001") then
        TDO_Config_Word <= Config_Init_Word2(to_integer(unsigned(shift_Count(3 downto 0)))); 
     elsif (shift_Count(7 downto 4) = "1010") then
        TDO_Config_Word <= Config_Init_Word3(to_integer(unsigned(shift_Count(3 downto 0))));
      elsif (shift_Count(7 downto 4) = "1011") then
        TDO_Config_Word <= Config_Init_Word4(to_integer(unsigned(shift_Count(3 downto 0))));
      elsif (C_PVR = 2) and (shift_Count(7 downto 4) = "1100") then
        TDO_Config_Word <= Config_Init_Word5(to_integer(unsigned(shift_Count(3 downto 0))));
      elsif (C_PVR = 2) and (shift_Count(7 downto 4) = "1101") then
        TDO_Config_Word <= Config_Init_Word6(to_integer(unsigned(shift_Count(3 downto 0))));
      else
        TDO_Config_Word <= Cache_Init_Word(to_integer(unsigned(shift_Count) - 32));        
      end if;      
    end process Config_TDO_Selecting;
  end generate Not_Use_SRL16;
  
  -----------------------------------------------------------------------------
  -- Handling Status Register
  -----------------------------------------------------------------------------

  -----------------------------------------------------------------------------
  -- Need to keep track of both the IMM instruction and the instruction after
  -- the IMM instruction
  -----------------------------------------------------------------------------
  Using_full_32_bit_immediates : process (Clk) is
  begin  -- process Using_full_32_bit_immediates
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset then                     -- synchronous reset (active true)
        Use_Imm_Reg_1 <= false;
      elsif (OF_PipeRun) then
        Use_Imm_Reg_1 <= Use_Imm_Reg;
      end if;
    end if;
  end process Using_full_32_bit_immediates;

  Capture_full_32_bit_immediates : process (Clk) is
  begin  -- process Capture_full_32_bit_immediates
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset then                     -- synchronous reset (active true)
        Full_32_bit   <= '0';
        Full_32_bit_1 <= '0';
      elsif( OF_PipeRun and ( Stop_Instr_Fetch_i = '0' ) ) then
        if (Use_Imm_Reg) then
          Full_32_bit <= '1';
        else
          Full_32_bit <= '0';
        end if;
        if (Use_Imm_Reg_1) then
          Full_32_bit_1<= '1';
        else
          Full_32_bit_1<= '0';
        end if;
      end if;
    end if;
  end process Capture_full_32_bit_immediates;

  Delay_slot_instruction : process (Clk) is
  begin  -- process Delay_slot_instruction
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset then                     -- synchronous reset (active true)
        delay_slot_instr_i <= '0';
      elsif (OF_PipeRun) and (Stop_Instr_Fetch_i = '0') then
        if (Branch_with_delay) then
          delay_slot_instr_i <= '1';
        else
          delay_slot_instr_i <= '0';