fsl_module.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

                 FSL_S_Data( 0*C_FSL_DATA_SIZE to  1*C_FSL_DATA_SIZE-1);
  end generate Num_FSL_16;
  
  -- Unused read signals.
  Unused_Read: for I in C_FSL_LINKS to C_MAX_FSL_LINKS - 1 generate
  begin
    FSL_S_Read(I)  <= '0';
  end generate Unused_Read;
  
  -- Area specific handling of data.
  Read_FSL_Area: if C_AREA_OPTIMIZED /= 0 generate
  begin
    Using_FPGA: if (C_TARGET /= RTL) generate    
    begin
      All_The_DFFs : for I in SIZE_DIFF to C_DATA_SIZE-1 generate
      begin
        FSL_Get_Data_FDRE : FDRE
          port map (
            Q  => FSL_Get_Data(I),            -- [out std_logic]
            C  => Clk,                       -- [in  std_logic]
            CE => '1',                       -- [in  std_logic]
            D  => FIFO_Data(I - SIZE_DIFF),  -- [in  std_logic]
            R  => Not_MB_Get_Op_i);          -- [in  std_logic]
      end generate All_The_DFFs;
  
      Not_Even_A_DFF : for I in 1 to SIZE_DIFF generate
      begin
        FSL_Get_Data(I-1) <= '0';
      end generate Not_Even_A_DFF;
    end generate Using_FPGA;
  
    Using_RTL: if (C_TARGET = RTL) generate
    begin
      Result_DFFS: process (Clk) is
      begin  -- process Result_DFFS
        if (Clk'event and Clk = '1') then
          FSL_Get_Data <= (others => '0');
          if (Not_MB_Get_Op_i = '0') then
            FSL_Get_Data(SIZE_DIFF to C_DATA_SIZE-1) <= FIFO_Data(0 to C_DATA_SIZE-1);
          end if;
        end if;
      end process Result_DFFS;
    end generate Using_RTL;
    
    FSL_S_Read_DFFS: process (Clk) is
    begin  -- process Result_DFFS
      if (Clk'event and Clk = '1') then
        if (Reset = '1') then
          FSL_S_Read(0 to C_FSL_LINKS-1)  <= (others=>'0');
        else
          FSL_S_Read(0 to C_FSL_LINKS-1)  <= FSL_S_Read_I(0 to C_FSL_LINKS-1);
        end if;
      end if;
    end process FSL_S_Read_DFFS;
    
  end generate Read_FSL_Area;
  
  
  -- Performance specific handling of read data & control path.
  Read_FSL_Performance: if C_AREA_OPTIMIZED = 0 generate
    signal fsl_get_succesful_happened   : boolean;
  begin
    -- Result load evaluation.
    MEM_EX_Result_Load <= (fsl_get_succesful_i = '1') or (EX_PipeRun and not fsl_get_succesful_happened);
  
    MEM_Ex_Result_Load_Handle: process (Clk) is
    begin  -- process MEM_Ex_Result_Load_Handle
      if Clk'event and Clk = '1' then     -- rising clock edge
        if Reset = '1' then               -- synchronous reset (active high)
          fsl_get_succesful_happened <= false;
        else
          if (fsl_get_succesful_i = '1') and (not EX_PipeRun) then
            fsl_get_succesful_happened <= true;
          elsif (EX_PipeRun) then
            fsl_get_succesful_happened <= false;          
          end if;       
        end if;
      end if;
    end process MEM_Ex_Result_Load_Handle;
    
    FSL_S_Read(0 to C_FSL_LINKS-1)  <= FSL_S_Read_I(0 to C_FSL_LINKS-1);
    FSL_Get_Data                    <= FIFO_Data;
    
  end generate Read_FSL_Performance;
  
  
  -----------------------------------------------------------------------------
  -- FSL Out handling
  -----------------------------------------------------------------------------

  FSL_Out_Handle : process (FSL_M_Full, FSL_Put, FSL_Put_Inhibit, fsl_put_no_i, FSL_Put_Break, FSL_Put_Test) is
  begin  -- process FSL_Out_Handle
    FSL_M_Write_I               <= (others => '0');
    FSL_M_Write_I(fsl_put_no_i) <= FSL_Put and not FSL_M_Full(fsl_put_no_i) and not FSL_Put_Inhibit and 
                                   ((not C_USE_EXTENDED_FSL_INSTR_S) or ((not FSL_Put_Break) and (not FSL_Put_Test)));
  end process FSL_Out_Handle;

  Put_Data: for I in 0 to C_MAX_FSL_LINKS - 1 generate
  begin
    FSL_M_Data(I*C_FSL_DATA_SIZE to (I+1)*C_FSL_DATA_SIZE-1) <= FSL_Put_Data;    
  end generate Put_Data;
  
  -- Expand control bit.
  FSL_M_Control                                <= (others => FSL_Put_Control);
  
  -- Unused write signals.
  Unused_Write: for I in C_FSL_LINKS to C_MAX_FSL_LINKS - 1 generate
  begin
    FSL_M_Write(I)  <= '0';
  end generate Unused_Write;
  
  -- Area specific handling of read data & control path.
  Write_FSL_Area: if C_AREA_OPTIMIZED /= 0 generate
  begin
    FSL_M_Write_DFFS: process (Clk) is
    begin  -- process Result_DFFS
      if (Clk'event and Clk = '1') then
        if (Reset = '1') then
          FSL_M_Write(0 to C_FSL_LINKS-1) <= (others=>'0');
        else
          FSL_M_Write(0 to C_FSL_LINKS-1) <= FSL_M_Write_I(0 to C_FSL_LINKS-1);
        end if;
      end if;
    end process FSL_M_Write_DFFS;
  end generate Write_FSL_Area;

  -- Performance specific handling of read data & control path.
  Write_FSL_Performance: if C_AREA_OPTIMIZED = 0 generate
  begin
    FSL_M_Write(0 to C_FSL_LINKS-1) <= FSL_M_Write_I(0 to C_FSL_LINKS-1);
    
  end generate Write_FSL_Performance;
  
  
  -----------------------------------------------------------------------------
  -- Handling Carry bit for the MSR during FSL instructions
  -----------------------------------------------------------------------------
  fsl_carry_i <= (FSL_Get and not FSL_S_Exists(fsl_get_no_i)) or
                 (FSL_Put and FSL_M_Full(fsl_put_no_i));

  -- Need to remember the correct carry value after the FSL instruction
  -- has finished but the pipeline hasn't moved yet
  FSL_Carry_Hold_Handle : process (Clk) is
  begin  -- process FSL_Carry_Hold_Handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
          fsl_carry_hold_value <= '0';
          fsl_carry_hold       <= '0';
      else
        if (FSL_Get = '1') then
          fsl_carry_hold_value <= not FSL_S_Exists(fsl_get_no_i);
          fsl_carry_hold       <= EX_MSR_Load_FSL_C;
        end if;
        if (FSL_Put = '1') then
          fsl_carry_hold_value <= FSL_M_Full(fsl_put_no_i);
          fsl_carry_hold       <= EX_MSR_Load_FSL_C;
        end if;
        if (EX_PipeRun or (FSL_Get_Break = '1') or (FSL_Put_Break = '1') ) then
          fsl_carry_hold_value <= '0';
          fsl_carry_hold       <= '0';
        end if;
      end if;
    end if;
  end process FSL_Carry_Hold_Handle;

  EX_FSL_Carry       <= FSL_Carry_i when (FSL_Get or FSL_Put) = '1' else fsl_carry_hold_value;
  EX_FSL_Write_Carry <= ( EX_MSR_Load_FSL_C or fsl_carry_hold ) and 
                        ( not( FSL_Get_Break or FSL_Put_Break ) or (not C_USE_EXTENDED_FSL_INSTR_S));

  -----------------------------------------------------------------------------
  -- Handling FSL_Control bit for the MSR 
  -----------------------------------------------------------------------------
  
  -- Need to remember the control error value after the FSL instruction
  -- has finished but the pipeline hasn't moved yet
  FSL_Control_Error_Handle : process (Clk) is
  begin  -- process FSL_Control_Error_Handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        fsl_control_error_hold_value <= '0';
      else
        if (FSL_Get = '1') then
          fsl_control_error_hold_value <= fsl_control_error_i;
        end if;
        if (EX_PipeRun) then
          fsl_control_error_hold_value <= '0';
        end if;
      end if;
    end if;
  end process FSL_Control_Error_Handle;

  fsl_control_error_i  <= ((FSL_S_Control(fsl_get_no_i) xor FSL_Get_Control)) and FSL_S_Exists(fsl_get_no_i);
  EX_FSL_Control_Error <= fsl_control_error_i when (FSL_Get = '1') else fsl_control_error_hold_value;

end architecture IMP;