fsl_module.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: fsl_module.vhd,v 1.2 2007/12/17 16:39:59 stefana Exp $
-------------------------------------------------------------------------------
-- fsl_module.vhd - Entity and architecture
--
--  ***************************************************************************
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--
-------------------------------------------------------------------------------
-- Filename:        fsl_module.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              fsl_module.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/12/17 16:39:59 $
--
-- History:
--   rikardw  2007-02-09    First Version (Merged fsl_module & fsl_module_gti)
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library Unisim;
use Unisim.vcomponents.all;

entity FSL_Module is
  generic (
    C_TARGET               : TARGET_FAMILY_TYPE;
    C_AREA_OPTIMIZED       : integer;
    C_FSL_LINKS            : integer;
    C_USE_EXTENDED_FSL_INSTR  : integer;
    C_MAX_FSL_LINKS        : natural;
    C_DATA_SIZE            : integer;
    C_FSL_DATA_SIZE        : integer
  );
  port (
    -- General
    Clk                  : in  std_logic;
    Reset                : in  std_logic;
    
    -- FSL Pipe control
    EX_PipeRun           : in  boolean;
    FSL_Stall            : out std_logic; -- A blocking FSL instruction is stalling pipeline
    
    -- FSL In Link
    FSL_S_Read           : out std_logic_vector(0 to C_MAX_FSL_LINKS-1);
    FSL_S_Data           : in  std_logic_vector(0 to C_MAX_FSL_LINKS*C_FSL_DATA_SIZE-1);
    FSL_S_Control        : in  std_logic_vector(0 to C_MAX_FSL_LINKS-1);
    FSL_S_Exists         : in  std_logic_vector(0 to C_MAX_FSL_LINKS-1);
    
    -- FSL Out Links
    FSL_M_Write          : out std_logic_vector(0 to C_MAX_FSL_LINKS-1);
    FSL_M_Control        : out std_logic_vector(0 to C_MAX_FSL_LINKS-1);
    FSL_M_Data           : out std_logic_vector(0 to C_MAX_FSL_LINKS * C_FSL_DATA_SIZE-1);
    FSL_M_Full           : in  std_logic_vector(0 to C_MAX_FSL_LINKS-1);
    
    -- Get signals
    FSL_Get              : in  std_logic;  -- A FSL get instruction
    FSL_Get_Test         : in  std_logic;  -- This is a test instruction.
    FSL_Get_Inhibit      : in  std_logic;  -- FSL Get must not execute (exceptions, ....)
    FSL_Get_Control      : in  std_logic;  -- The get control bit from the FSL instruction
    FSL_Get_Blocking     : in  std_logic;  -- The FSL get instruction is blocking
    FSL_Get_Break        : in  std_logic;  -- The FSL is breaked
    FSL_Get_No           : in  natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
    FSL_Get_Data         : out std_logic_vector(0 to C_DATA_SIZE-1);  -- Data that is received
    FSL_Get_Succesful    : out std_logic;  -- The FSL get was succesful
    EX_FSL_Control_Error : out std_logic;  -- A FSL Get control bit mismatch has occured
    
    -- Put signals
    FSL_Put              : in  std_logic;  -- A FSL put instruction
    FSL_Put_Test         : in  std_logic;  -- This is a test instruction.
    FSL_Put_Inhibit      : in  std_logic;  -- FSL Put must not execute (exceptions, ....)
    FSL_Put_Control      : in  std_logic;  -- The put control bit from the FSL instruction
    FSL_Put_Blocking     : in  std_logic;  -- The FSL put instruction is blocking
    FSL_Put_Break        : in  std_logic;  -- The FSL is breaked
    FSL_Put_No           : in  natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
    FSL_Put_Data         : in  std_logic_vector(0 to C_DATA_SIZE-1);  -- Data to put
    FSL_Put_Succesful    : out std_logic;  -- The FSL put was succesful
    
    -- Carry & result
    Not_MB_Get_Op        : in  std_logic;
    Dbg_Inhibit_EX       : in  std_logic;
    EX_MSR_Load_FSL_C    : in  std_logic;
    EX_FSL_Write_Carry   : out std_logic;
    EX_FSL_Carry         : out std_logic;
    MEM_EX_Result_Load   : out boolean
  );
end entity FSL_Module;

architecture IMP of FSL_Module is

  function int2std (val : integer) return std_logic is
  begin  -- function int2std
    if (val = 0) then
      return '0';
    else
      return '1';
    end if;
  end function int2std;

  constant SIZE_DIFF : natural := (C_DATA_SIZE - C_FSL_DATA_SIZE);
  constant C_USE_EXTENDED_FSL_INSTR_S : std_logic:= int2std(C_USE_EXTENDED_FSL_INSTR);
  
  signal FIFO_Data : std_logic_vector(0 to C_FSL_DATA_SIZE-1);

  signal get_stall                    : std_logic;
  signal put_stall                    : std_logic;

  signal fsl_get_no_i                 : natural range 0 to C_FSL_LINKS-1;
  signal fsl_put_no_i                 : natural range 0 to C_FSL_LINKS-1;

  signal fsl_get_succesful_i          : std_logic;

  signal fsl_control_error_i          : std_logic;
  signal fsl_control_error_hold_value : std_logic;
  
  signal fsl_carry_i                  : std_logic;
  signal fsl_carry_hold               : std_logic;
  signal fsl_carry_hold_value         : std_logic;

  signal FSL_S_Read_I                 : std_logic_vector(0 to C_MAX_FSL_LINKS-1);
  signal FSL_M_Write_I                : std_logic_vector(0 to C_MAX_FSL_LINKS-1);

  signal not_MB_Get_Op_i : std_logic;
  
begin  -- architecture IMP

  -----------------------------------------------------------------------------
  -- FSL General & Successful Handling
  -----------------------------------------------------------------------------
  
  fsl_get_no_i        <= FSL_Get_No;
  fsl_put_no_i        <= FSL_Put_No;
    
  get_stall           <= FSL_Get_Blocking and FSL_Get and (not FSL_S_Exists(fsl_get_no_i)) and 
                         ( (not C_USE_EXTENDED_FSL_INSTR_S) or (not FSL_Get_Break) );
  put_stall           <= FSL_Put_Blocking and FSL_Put and FSL_M_Full(fsl_put_no_i) and 
                         ( (not C_USE_EXTENDED_FSL_INSTR_S) or (not FSL_Put_Break) );

  FSL_Stall           <= get_stall or put_stall;

  fsl_get_succesful_i <= not FSL_Get_Inhibit and FSL_Get and (FSL_S_Exists(fsl_get_no_i) or (C_USE_EXTENDED_FSL_INSTR_S and FSL_Get_Break));
  FSL_Get_Succesful   <= fsl_get_succesful_i;
  
  FSL_Put_Succesful   <= not FSL_Put_Inhibit and FSL_Put and ((not FSL_M_Full(fsl_put_no_i)) or (C_USE_EXTENDED_FSL_INSTR_S and FSL_Put_Break));