read_data_mux_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: read_data_mux_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- MicroBlaze - entity/architecture
-------------------------------------------------------------------------------
-- ** Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc.
-- **
-- ** Unmodified source code is guaranteed to place and route,
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-------------------------------------------------------------------------------
-- Filename:        read_data_mux.vhd
-- Version:         v1.00a
-- Description:     MicroBlaze embedded processor core
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              read_data_mux.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity read_data_mux is
  
  generic (
    C_USE_D_EXT  : boolean := false;
    C_USE_D_LMB  : boolean := false;
    C_USE_DCACHE : boolean := false
    );
  port (
    WB_DLMB_valid_read_data   : in  DATA_TYPE;
    WB_DLMB_data_strobe       : in  std_logic;
    WB_DExt_Read_Data         : in  DATA_TYPE;
    WB_DExt_data_strobe       : in  std_logic;
    WB_DCache_valid_read_data : in  DATA_TYPE;
    WB_DataBus_Read_Data      : out DATA_TYPE
    );
end entity read_data_mux;

architecture IMP of read_data_mux is
  signal enable_ext_databus    : DATA_TYPE;
  signal enable_lmb_databus    : DATA_TYPE;
  signal enable_dcache_databus : DATA_TYPE;
begin  -- IMP

  enable_ext_dataBus    <= (others => '1') when (WB_DExt_data_strobe = '1') and C_USE_D_EXT else (others => '0');
  enable_lmb_databus    <= (others => '1') when C_USE_D_LMB                                 else (others => '0');
  enable_dcache_databus <= (others => '1') when C_USE_DCACHE                                else (others => '0');

  WB_DataBus_Read_Data <= (WB_DLMB_valid_read_data and enable_lmb_databus) or
                          (WB_DCache_valid_read_data and enable_dcache_databus) or
                          (WB_DExt_read_data and enable_ext_dataBus);

end IMP;