register_file.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: register_file.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Register_File -entity/architecture 
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        register_file.vhd
-- Version:         v1.00a
-- Description:     Implements the Register File
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              register_file.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Register_File is

  generic (
    C_DATA_SIZE : natural range 4 to 64 := 32;
    C_TARGET    : TARGET_FAMILY_TYPE
    );
  port (
    Clk        : in  std_logic;
    Reset      : in  boolean;
    Write_Addr : in  std_logic_vector(0 to 4);
    Reg1_Addr  : in  std_logic_vector(0 to 4);
    Reg2_Addr  : in  std_logic_vector(0 to 4);
    Reg_Write  : in  boolean;
    EX_Result  : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
    Reg1_Data  : out std_logic_vector(0 to C_DATA_SIZE-1);
    Reg2_Data  : out std_logic_vector(0 to C_DATA_SIZE-1)
    );

end entity Register_File;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of Register_File is

  component Register_File_Bit is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Clk        : in  std_logic;
      -- Reset      : in  boolean;
      Write_Addr : in  std_logic_vector(0 to 4);
      Reg1_Addr  : in  std_logic_vector(0 to 4);
      Reg2_Addr  : in  std_logic_vector(0 to 4);
      Reg_Write  : in  boolean;
      EX_Result  : in  std_logic;
      Data_Write : out std_logic;
      Reg1_Data  : out std_logic;
      Reg2_Data  : out std_logic);
  end component Register_File_Bit;

begin  -- IMP

  Using_FPGA : if (C_TARGET /= RTL) generate
    
    Gen_RegFile : for I in C_DATA_SIZE-1 downto 0 generate
      Register_File_Bit_I : Register_File_Bit
        generic map (
          C_TARGET => C_TARGET)
        port map (
          Clk        => Clk,            -- [in]
          Write_Addr => Write_Addr,     -- [in]
          Reg1_Addr  => Reg1_Addr,      -- [in]
          Reg2_Addr  => Reg2_Addr,      -- [in]
          Reg_Write  => Reg_Write,      -- [in]
          EX_Result  => EX_Result(I),   -- [in]
          Data_Write => Data_Write(I),  -- [out]
          Reg1_Data  => Reg1_Data(I),   -- [out]
          Reg2_Data  => Reg2_Data(I));  -- [out]

    end generate Gen_RegFile;
  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate

    type   REG_FILE_TYPE is array(0 to 31) of std_logic_vector(0 to C_DATA_SIZE-1);
    signal Reg_File : REG_FILE_TYPE := (others => (others => '0'));

  begin
    
    Reg_File_Handle : process (Clk) is
    begin  -- process Reg_File_Handle
      if Clk'event and Clk = '1' then   -- rising clock edge
        if (Reg_Write) then
          Reg_File(to_integer(unsigned(Write_Addr))) <= EX_Result;
        end if;
      end if;
    end process Reg_File_Handle;

    Reg1_Data  <= Reg_File(to_integer(unsigned(Reg1_Addr)));
    Reg2_Data  <= Reg_File(to_integer(unsigned(Reg2_Addr)));
    Data_Write <= Reg_File(to_integer(unsigned(Write_Addr)));
  end generate Using_RTL;
  
end architecture IMP;