iplb_interface.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: iplb_interface.vhd,v 1.2 2008/01/16 15:46:49 stefana Exp $
-------------------------------------------------------------------------------
-- IOPB_Interface - entity/architecture
-------------------------------------------------------------------------------
--
-- ****************************************************************************
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-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc.
-- **
-- ** Unmodified source code is guaranteed to place and route,
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        iopb_interface.vhd
-- Description:     Instruction side OPB interface for MicroBlaze
--
-------------------------------------------------------------------------------
-- Structure: 
--
--              iopb_interface.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity IPLB_Interface is
  generic (
    C_IPLB_DWIDTH :    natural := 32
    );
  port (
    -- global signals
    Clk         : in std_logic;
    Reset       : in std_logic;

    -- PLB signals
    IPLB_M_ABort      : out std_logic;
    IPLB_M_ABus       : out std_logic_vector(0 to 31);
    IPLB_M_UABus      : out std_logic_vector(0 to 31);
    IPLB_M_BE         : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
    IPLB_M_busLock    : out std_logic;
    IPLB_M_lockErr    : out std_logic;
    IPLB_M_MSize      : out std_logic_vector(0 to 1);
    IPLB_M_priority   : out std_logic_vector(0 to 1);
    IPLB_M_rdBurst    : out std_logic;
    IPLB_M_request    : out std_logic;
    IPLB_M_RNW        : out std_logic;
    IPLB_M_size       : out std_logic_vector(0 to 3);
    IPLB_M_TAttribute : out std_logic_vector(0 to 15);
    IPLB_M_type       : out std_logic_vector(0 to 2);
    IPLB_M_wrBurst    : out std_logic;
    IPLB_M_wrDBus     : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
    IPLB_MBusy        : in  std_logic;
    IPLB_MRdErr       : in  std_logic;
    IPLB_MWrErr       : in  std_logic;
    IPLB_MIRQ         : in  std_logic;
    IPLB_MWrBTerm     : in  std_logic;
    IPLB_MWrDAck      : in  std_logic;
    IPLB_MAddrAck     : in  std_logic;
    IPLB_MRdBTerm     : in  std_logic;
    IPLB_MRdDAck      : in  std_logic;
    IPLB_MRdDBus      : in  std_logic_vector(0 to C_IPLB_DWIDTH-1);
    IPLB_MRdWdAddr    : in  std_logic_vector(0 to 3);
    IPLB_MRearbitrate : in  std_logic;
    IPLB_MSSize       : in  std_logic_vector(0 to 1);
    IPLB_MTimeout     : in  std_logic;
    
    -- Local Bus signals
    IPLB_Data_Strobe  : out std_logic;
    IPLB_Data         : out DATA_TYPE;
    IB_Addr           : in  DATA_TYPE;
    IB_Addr_Strobe    : in  std_logic;
    IB_Fetch          : in  std_logic;
    IPLB_Drop_Request : in  std_logic;

    -- other signals
    IPLB_Exception     : out std_logic
    );

end entity IPLB_Interface;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of IPLB_Interface is

  signal instr_addr           : DATA_TYPE;
  signal ib_addr_strobe_d1    : std_logic;
  signal mem_access_completed : std_logic;

begin

  -----------------------------------------------------------------------------
  -- Constant values on PLB signals
  -----------------------------------------------------------------------------  
  IPLB_M_ABort      <= '0';             -- Abort is not used and is not
                                        -- available in Xilinx subset of PLB v4.6
  IPLB_M_UABus      <= (others => '0');  -- Not used in Xilinx subset of PLB v4.6
  IPLB_M_busLock    <= '0';    -- Not used in Xilinx subset of PLB v4.6
  IPLB_M_lockErr    <= '0';    -- Not used in Xilinx subset of PLB v4.6
  IPLB_M_priority   <= "00";   -- Not used in Xilinx subset of PLB v4.6
  IPLB_M_rdBurst    <= '0';    -- Not used by MicroBlaze, no burst handling
  IPLB_M_TAttribute <= (others => '0');  -- Not used in Xilinx subset of PLB v4.6
  IPLB_M_type       <= "000";  -- Not used in Xilinx subset of PLB v4.6
  IPLB_M_wrBurst    <= '0';    -- Not used by MicroBlaze, no burst handling

  IPLB_M_MSize <= "00";    -- MicroBlaze only do 32-bit data transfers
  IPLB_M_size  <= "0000";               -- MicroBlaze only request 32-bit
                                        -- single beat transfers

  -----------------------------------------------------------------------------
  -- Just drive the PLB signals
  -- no requirement to drive to "0" while not requesting access
  -----------------------------------------------------------------------------
  IPLB_M_ABus   <= instr_addr;
  IPLB_M_RNW    <= '1';                 -- Always Reading
  IPLB_M_wrDBus <= (others => '0');     -- Never write values
  IPLB_M_BE     <= (others => '1');     -- Always word accesses
  
  -----------------------------------------------------------------------------
  -- Capture internal instruction bus
  -----------------------------------------------------------------------------
  Capture_IBus : process (Clk)
  begin  -- process Capture_IBus
    if Clk'event and Clk = '1' then     -- rising clock edge
      ib_addr_strobe_d1 <= IB_Addr_Strobe;
      if IB_Addr_Strobe = '1' then
        instr_addr      <= IB_Addr;
      end if;
    end if;
  end process Capture_IBus;

  -----------------------------------------------------------------------------
  -- Arbitration signalling
  -----------------------------------------------------------------------------
  PLB_Request : process (Clk) is
  begin  -- process PLB_Request
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        IPLB_M_request <= '0';
      else
        -- A new request is request and Cache or LMB has not already responded
        -- and the transfer is not finished
        if ((ib_addr_strobe_d1 = '1') and (IPLB_Drop_Request = '0')) then
          IPLB_M_request <= '1';
        end if;
        -- Timeout => end request and signalling databus exception
        if (IPLB_MTimeout = '1') then
          IPLB_M_request <= '0';
        end if;
        -- Address phase is acknowledge
        if (IPLB_MAddrAck = '1') then
          IPLB_M_request <= '0';
        end if;
      end if;
    end if;
  end process PLB_Request;

  -----------------------------------------------------------------------------
  -- Instruction OPB access completion
  -----------------------------------------------------------------------------
  IPLB_Data_Strobe <= mem_access_completed;

  access_completion_DFF : process (Clk)
  begin
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then
        IPLB_Data            <= (others => '0');
        IPLB_Exception       <= '0';
        mem_access_completed <= '0';
      else
        mem_access_completed <= IPLB_MRdDAck or IPLB_MWrDAck or IPLB_MTimeout;
        IPLB_Exception       <= IPLB_MRdErr or IPLB_MWrErr or IPLB_MTimeout;
        IPLB_Data            <= IPLB_MRdDBus(0 to 31);
      end if;
    end if;
  end process access_completion_DFF;

end architecture IMP;