data_flow_logic_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: data_flow_logic_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- data_flow_logic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: data_flow.vhd
-- Version: v1.00a
-- Description: Logic for Moving the data through the processor
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              data_flow_logic.vhd
--
-------------------------------------------------------------------------------
-- Author:          stassart
-- History:
--   BJS    2005-03-31    - First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
--
--    Clk                     -- Clock
--    Reset                   -- internal reset
--
--    OF_PipeRun              -- Move the operand fetch stage
--    EX_PipeRun              -- Move the execute stage
--    MEM_PipeRun             -- Move the memory stage
--
--    EX_Op1                  -- Operand 1 in EX stage
--    EX_Op2                  -- Operand 2 in EX stage
--
--    EX_Op1_2LSb             -- 2 least significants bits of EX stage operand 1
--    EX_Op2_2LSb             -- 2 least significants bits of EX stage operand 2
--
--    EX_Fwd                  -- Execute stage forwarding
--    MEM_Fwd                 -- Memory stage forwarding
--
--    MEM_EX_Result           -- EX stage result in MEM stage
--    WB_MEM_Result           -- MEM stage result in WB stage
--
--    EX_UnAlign_2LSb         -- EX stage unaligned bytes and doublets
--    WB_UnAlign_2LSb         -- WB stage unaligned bytes and doublets
--
--    WB_Byte_Access          -- Read on data bus is 8-bits
--    WB_Quadlet_Access       -- Read on data bus is 32-bits
--
-------------------------------------------------------------------------------
entity Data_Flow_Logic is
  generic (
    C_MAX_FSL_LINKS  : natural
  );
  port (
    Clk                 : in  std_logic;
    Reset               : in  std_logic;

    OF_PipeRun          : in  boolean;
    EX_PipeRun          : in  boolean;
    MEM_PipeRun         : in  boolean;

    EX_Op1              : in  DATA_TYPE;
    EX_Op2              : in  DATA_TYPE;

    EX_Op1_2LSb         : out slv_0to1;
    EX_Op2_2LSb         : out slv_0to1;

    EX_Fwd              : in  DATA_TYPE;
    MEM_Fwd             : in  DATA_TYPE; 

    EX_FSL_No           : in  natural range 0 to C_MAX_FSL_LINKS-1;
    WB_FSL_No           : out natural range 0 to C_MAX_FSL_LINKS-1;
    
    EX_Is_BS_Instr      : in  boolean;
    EX_Is_Div_Instr     : in  boolean;
    MEM_EX_Result_Load  : in  boolean;
    MEM_Sel_MEM_Res     : in  boolean;
    MEM_EX_Result       : out DATA_TYPE; 
    WB_MEM_Result       : out DATA_TYPE;

    EX_Not_Mul_Op       : in boolean;
    MEM_Not_Mul_Op      : out boolean;

    EX_Not_FPU_Op       : in  boolean;
    MEM_Not_FPU_Op      :  out boolean;

    EX_UnAlign_2LSb     : in  slv_0to1;
    WB_UnAlign_2LSb     : out slv_0to1;

    WB_Byte_Access      : in  boolean;
    WB_Quadlet_Access   : in  boolean
  );
end entity Data_Flow_Logic;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of Data_Flow_Logic is
  signal mem_unalign_2lsb       : slv_0to1;

  signal mem_op1_byte_sign      : std_logic;
  signal mem_op1_doublet_sign   : std_logic;
  signal wb_op1_byte_sign       : std_logic;
  signal wb_op1_doublet_sign    : std_logic;

  signal mem_FSL_No             : natural range 0 to C_MAX_FSL_LINKS-1;
  
begin

  --***************************************************************************
  --***************************************************************************
  --                   Instruction Fetch (IF) stage handling
  --***************************************************************************
  --***************************************************************************

  --***************************************************************************
  --***************************************************************************
  --                   Operand Fetch (OF) stage handling
  --***************************************************************************
  --***************************************************************************

  --***************************************************************************
  --***************************************************************************
  --                   Execution (EX) stage handling
  --***************************************************************************
  --***************************************************************************
  
  ----------------------------------------
  -- 2 least significant bits in EX stage Op1 and Op2
  ----------------------------------------
  EX_Op1_2LSb <= EX_Op1(DATA_TYPE'right-1 to DATA_TYPE'right);
  EX_Op2_2LSb <= EX_Op2(DATA_TYPE'right-1 to DATA_TYPE'right);

  --***************************************************************************
  --***************************************************************************
  --                   Memory (MEM) stage handling
  --***************************************************************************
  --***************************************************************************

  ----------------------------------------
  -- mem_FSL_No_DFF
  -- FSL channel from EX stage registered into MEM stage
  ----------------------------------------
  MEM_FSL_No_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then -- rising clock edge
      if Reset = '1' then
        mem_FSL_No <= 0;
      elsif(EX_PipeRun) then
        mem_FSL_No <= EX_FSL_No;
      end if;
    end if;
  end process MEM_FSL_No_DFF;

  ----------------------------------------
  -- MEM_EX_Res_DFF
  -- result from EX stage registered into MEM stage
  ----------------------------------------
  MEM_EX_Result_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then -- rising clock edge
      if Reset = '1' or EX_Is_BS_Instr or EX_Is_Div_Instr then
        MEM_EX_Result <= (others => '0');
      elsif (MEM_EX_Result_Load) then
        MEM_EX_Result <= EX_Fwd;
      end if;
    end if;
  end process MEM_EX_Result_DFF;

  ----------------------------------------
  -- MEM_Unalign_2LSb_DFF
  -- byte_doublet unalign from EX stage registered into MEM stage
  ----------------------------------------
  MEM_Unalign_2LSb_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then -- rising clock edge
      if Reset = '1' then
        mem_unalign_2lsb <= (others => '0');
      elsif (EX_PipeRun) then
        mem_unalign_2lsb <= ex_unalign_2lsb;
      end if;
    end if;
  end process MEM_Unalign_2LSb_DFF;

  ----------------------------------------
  -- MEM_Sign_Bits_DFF
  -- MEM stage sign bits
  ----------------------------------------
  MEM_Sign_Bits_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then -- rising clock edge
      if Reset = '1' then
        mem_op1_byte_sign    <= '0';
        mem_op1_doublet_sign <= '0';
      elsif (EX_PipeRun) then
        mem_op1_byte_sign    <= EX_Op1(BYTE_SIGN_POS);
        mem_op1_doublet_sign <= EX_Op1(DOUBLET_SIGN_POS);
      end if;
    end if;
  end process MEM_Sign_Bits_DFF;

  Mem_not_mul_op_DFF: process (Clk) is
  begin  -- process Mem_not_mul_op_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        MEM_Not_Mul_Op <= true;
      elsif (EX_PipeRun) then
        MEM_Not_Mul_Op <= EX_Not_Mul_Op;        
      end if;
    end if;
  end process Mem_not_mul_op_DFF;
  
  Mem_not_FPU_op_DFF: process (Clk) is
  begin  -- process Mem_not_FPU_op_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        MEM_Not_FPU_Op <= true;
      elsif (EX_PipeRun) then
        MEM_Not_FPU_Op <= EX_Not_FPU_Op;        
      end if;
    end if;
  end process Mem_not_FPU_op_DFF;
  
  --***************************************************************************
  --***************************************************************************
  --                   Write Back (WB) stage handling
  --***************************************************************************
  --***************************************************************************

  ----------------------------------------
  -- WB_FSL_No_DFF
  -- FSL channel from MEM stage registered into WB stage
  ----------------------------------------
  WB_FSL_No_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then -- rising clock edge
      if Reset = '1' then
        WB_FSL_No <= 0;
      elsif (MEM_PipeRun) then
        WB_FSL_No <= mem_FSL_No;
      end if;
    end if;
  end process WB_FSL_No_DFF;

  ----------------------------------------
  -- WB_Mem_Result_DFF
  -- result from MEM stage registered into WB stage
  ----------------------------------------
  WB_MEM_Result_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then -- rising clock edge
      if Reset = '1' or not MEM_Sel_MEM_Res then
        WB_MEM_Result <= (others => '0');
      elsif (MEM_PipeRun) then
        WB_MEM_Result <= MEM_Fwd;
      end if;
    end if;
  end process WB_MEM_Result_DFF;

  ----------------------------------------
  -- WB_Unalign_2LSb_DFF
  -- byte_doublet unalign from MEM stage registered into WB stage
  ----------------------------------------
  WB_Unalign_2LSb_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then -- rising clock edge
      if Reset = '1' then
        WB_UnAlign_2LSb <= (others => '0');
      elsif (MEM_PipeRun) then
        WB_UnAlign_2LSb <= mem_unalign_2lsb;
      end if;
    end if;
  end process WB_Unalign_2LSb_DFF;

  ----------------------------------------
  -- WB_Sign_Bits_DFF
  -- WB stage sign bits
  ----------------------------------------
  WB_Sign_Bits_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then -- rising clock edge
      if Reset = '1' then
        wb_op1_byte_sign    <= '0';
        wb_op1_doublet_sign <= '0';
      elsif (MEM_PipeRun) then
        wb_op1_byte_sign    <= mem_op1_byte_sign;
        wb_op1_doublet_sign <= mem_op1_doublet_sign;
      end if;
    end if;
  end process WB_Sign_Bits_DFF;


end architecture IMP;