address_hit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: address_hit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- address_hit.vhd
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        address_hit.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              address_hit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2001-10-30    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;

entity address_hit is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE;
    C_FIRST  : boolean := false;
    No_Bits  : natural := 32);
  port (
    Address       : in  std_logic_vector(0 to No_Bits-1);
    Armed         : in  std_logic;
    TClk          : in  std_logic;
    TDI           : in  std_logic;
    SRL16_En      : in  std_logic;
    Single_Step_N : in  std_logic;
    Hit           : out std_logic
    );
end entity address_hit;

library unisim;
use unisim.vcomponents.all;

architecture IMP of address_hit is

  signal carry      : std_logic_vector(0 to 8);
  signal SRL16_MC15 : std_logic_vector(0 to 8);
  signal SRL16_Sel  : std_logic_vector(0 to 7);
 
begin  -- architecture IMP

  Using_FPGA : if (C_TARGET /= RTL) generate

      SRL16_MC15(8) <= TDI;
      
      MUXCY_Pre : MUXCY
        port map (
          DI => '0',                    -- [in  std_logic]
          CI => '1',                    -- [in  std_logic]
          S  => armed,                  -- [in  std_logic]
          O  => carry(8));              -- [out std_logic]

      Compare : for I in 7 downto 0 generate
        SRLC16E_I : SRLC16E
          port map (
            CE  => SRL16_En,            -- [in  std_logic]
            D   => SRL16_MC15(I+1),       -- [in  std_logic]
            Clk => TClk,                -- [in  std_logic]
            A0  => Address(31-I*4),     -- [in  std_logic]
            A1  => Address(30-I*4),     -- [in  std_logic]
            A2  => Address(29-I*4),     -- [in  std_logic]
            A3  => Address(28-I*4),     -- [in  std_logic]
            Q   => SRL16_Sel(I),        -- [out std_logic]
            Q15 => SRL16_MC15(I));    -- [out std_logic]

        MUXCY_I : MUXCY
          port map (
            DI => '0',                  -- [in  std_logic]
            CI => carry(I+1),             -- [in  std_logic]
            S  => SRL16_Sel(I),         -- [in  std_logic]
            O  => carry(I));          -- [out std_logic]
      end generate Compare;

    The_First_BreakPoints : if (C_FIRST) generate
      MUXCY_Post : MUXCY
        port map (
          DI => '1',                    -- [in  std_logic]
          CI => carry(carry'left),      -- [in  std_logic]
          S  => Single_Step_N,          -- [in  std_logic]
          O  => hit);                   -- [out std_logic]

    end generate The_First_BreakPoints;

      Not_The_First : if (not C_FIRST) generate
        hit <= carry(carry'left);      
    end generate Not_The_First;

  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate
    subtype SRL16_TYPE is std_logic_vector(0 to 15);
    type    SRL16_ARRAY_TYPE is array (0 to 7) of SRL16_TYPE;

    signal srl16_Array : SRL16_ARRAY_TYPE;
  begin

    Load_SRL16s : process (TClk) is
    begin  -- process Load_SRL16s
      if TClk'event and TClk = '1' then  -- rising clock edge
        if (SRL16_En = '1') then
          for I in 7 downto 0 loop
            if (I /= 7) then
              srl16_Array(I) <= srl16_Array(I+1)(15) & srl16_Array(I)(0 to 14);
            else
              srl16_Array(I) <= TDI & srl16_Array(I)(0 to 14);
            end if;
          end loop;  -- I
        end if;
      end if;
    end process Load_SRL16s;

    Hit_Detect : process (srl16_Array, Armed, Address, Single_Step_N) is
      variable local_hit  : std_logic;
      variable temp_srl16 : SRL16_TYPE;
    begin  -- process Hit_Detect
      if (Single_Step_N = '0') and C_FIRST then
        hit <= '1';
      elsif (Armed = '1') then
        local_hit := '1';
        for I in 0 to 7 loop
          temp_srl16 := srl16_Array(I);
          if temp_srl16(to_integer(unsigned(Address(I*4 to I*4+3)))) = '0' then
            local_hit := '0';
          end if;
        end loop;  -- I
        hit <= local_hit;
      else
        hit <= '0';
      end if;
    end process Hit_Detect;

  end generate Using_RTL;
end architecture IMP;