mmu_types_pkg.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: mmu_types_pkg.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- MMU_Types -  package
--
-- ****************************************************************************
-- ** Copyright(C) 2006 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc.
-- **
-- ** Unmodified source code is guaranteed to place and route,
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        mmu_types_pkg.vhd
--
-- Description:     Package with types and constants supporting MicroBlaze MMU
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              mmu_types_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author:          stefana
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   stefana 2006-10-23    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

package MMU_Types is

  subtype TLB_Index_Type is std_logic_vector(0 to 5);

  -- TLBHI types and constants
  subtype TLBHI_Type   is std_logic_vector(0 to 35);

  subtype TAG_Type     is std_logic_vector(0  to 21);

  subtype TAG_MSB_Type is std_logic_vector(0  to 7);
  subtype TAG_LSB_Type is std_logic_vector(8  to 21);

  subtype SIZE_Type    is std_logic_vector(22 to 24);

  constant C_VALID     : integer := 25;

  subtype SIZE_Addr_Type is std_logic_vector(8 to 21);
  type SIZE_Mask_Type is array (0 to 7) of SIZE_Addr_Type;

  constant C_SIZE_MASK : SIZE_Mask_Type := (0 => "11111111111111",
                                            1 => "11111111111100",
                                            2 => "11111111110000",
                                            3 => "11111111000000",
                                            4 => "11111100000000",
                                            5 => "11110000000000",
                                            6 => "11000000000000",
                                            7 => "00000000000000");

  subtype TID_Type is std_logic_vector(28 to 35);

  -- TLBLO types and constants
  subtype RPN_Type  is std_logic_vector(0  to 21);
  constant C_EX     : integer := 22;
  constant C_WR     : integer := 23;
  subtype ZSEL_Type is std_logic_vector(24 to 27);
  constant C_I      : integer := 29;
  constant C_G      : integer := 31;

end package MMU_Types;