microblaze.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      C_DCACHE_ADDR_TAG       : integer;
      C_DCACHE_USE_FSL        : integer;
      C_ALLOW_DCACHE_WR       : integer;
      C_DCACHE_LINE_LEN       : integer;
      C_DCACHE_BYTE_SIZE      : integer;
      C_DCACHE_ALWAYS_USED    : integer;
      C_ICACHE_BASEADDR       : std_logic_vector(0 to 31);
      C_ICACHE_HIGHADDR       : std_logic_vector(0 to 31);
      C_DCACHE_BASEADDR       : std_logic_vector(0 to 31);
      C_DCACHE_HIGHADDR       : std_logic_vector(0 to 31);
      C_USE_MMU               : integer;
      C_MMU_DTLB_SIZE         : integer;
      C_MMU_ITLB_SIZE         : integer;
      C_MMU_TLB_ACCESS        : integer;
      C_MMU_ZONES             : integer;
      C_RESET_MSR             : MSR_TYPE);
    port (

      -- global ports
      Clk        : in std_logic;
      Reset      : in boolean;
      OF_PipeRun : in boolean;

      -- ports to "Register_File_I"
      Write_Addr : in  std_logic_vector(0 to 4);
      Reg1_Addr  : in  std_logic_vector(0 to 4);
      Reg2_Addr  : in  std_logic_vector(0 to 4);
      Reg_Write  : in  boolean;
      Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);

      -- ports to "Operand_Select_I"
      Imm_Value               : in  std_logic_vector(0 to 15);
      OpSel1_PC               : in  boolean;
      OpSel1_SPR              : in  boolean;
      -- OpSel1_FSR              : in  boolean;
      OpSel2_Imm              : in  boolean;
      Take_Ext_BRK            : in  boolean;
      Take_Exception          : in  boolean;
      Take_Interrupt          : in  boolean;
      Store_PC_For_Intr       : in  boolean;
      Store_PC_For_Intr_NoImm : in  boolean;
      Res_Forward1            : in  boolean;
      Res_Forward2            : in  boolean;
      Imm_Instr               : in  boolean;
      Use_Imm_Reg             : in  boolean;
      MFS_Reg_Sel             : in  std_logic_vector(0 to 2);
      BTR                     : in  BTR_TYPE;
      EAR                     : in  EAR_TYPE;
      EDR                     : in  EDR_TYPE;
      ESR                     : in  ESR_TYPE;
      word_r1_r2_unalignment  : out std_logic;
      word_r1_imm_unalignment : out std_logic;
      halfword_unalignment    : out std_logic;

      -- ports to "ALU_I"
      ALU_Op        : in  std_logic_vector(0 to 1);
      Compare_Instr : in  std_logic;
      Unsigned_Op   : in  std_logic;
      Carry_In      : in  std_logic;
      ALU_Carry     : out std_logic;
      Data_Addr     : out std_logic_vector(0 to C_DATA_SIZE-1);

      -- ports to "Shift_Logic_Module_I"
      Sext8           : in  boolean;
      Sext16          : in  boolean;
      -- Sext32          : in  boolean;
      PCMP_Instr      : in  boolean;
      Shift_Carry_In  : in  std_logic;
      Sign_Extend     : in  boolean;
      Shift_Oper      : in  std_logic_vector(0 to 1);
      Logic_Oper      : in  std_logic_vector(0 to 1);
      Select_Logic    : in  boolean;
      Shift_Carry_Out : out std_logic;

      -- ports to "Result_Mux_I"
      Result_Sel   : in std_logic_vector(0 to 1);
      Doublet_Read : in boolean;
      Quadlet_Read : in boolean;
      -- Hexlet_Read  : in boolean;
      Data_Read       : in std_logic_vector(0 to C_DATA_SIZE-1);
      EX_Not_Mul_Op   : in boolean;
      EX_Mulh_Instr   : in boolean;
      EX_Mulhu_Instr  : in boolean;
      EX_Mulhsu_Instr : in boolean;

      -- ports to "Barrel_Shifter_I"
      Arith_Shift   : in std_logic;
      Left_Shift    : in std_logic;
      Not_Barrel_Op : in std_logic;

      -- ports to "Zero_Detect_I"
      Reg_Test_Equal   : in  std_logic;
      Reg_Test_Equal_N : in  std_logic;
      Reg_zero         : out std_logic;
      Reg_neg          : out std_logic;

      -- ports to "MSR_Reg_I"
      Write_Carry        : in  boolean;
      New_Carry          : in  std_logic;
      MTSMSR_Write       : in  boolean;
      Disable_Interrupts : in  boolean;
      Enable_Interrupts  : in  boolean;
      Set_BIP            : in  boolean;
      Reset_BIP          : in  boolean;
      BIP_Active         : out boolean;
      Carry              : out std_logic;
      Enable_Interrupt   : out boolean;
      Enable_BusLock     : out boolean;
      MSRxxx_Instr       : in  boolean;
      MSRclr_Instr       : in  boolean;

      Disable_Exceptions : in  boolean;
      Enable_Exceptions  : in  boolean;
      Exceptions_Enabled : out boolean;
      Set_EIP            : in  boolean;
      Reset_EIP          : in  boolean;
      EIP_Active         : out boolean;

      -- ports to "PC_Module_I"
      PC_Incr     : in  boolean;
      Jump        : in  boolean;
      PC_Write    : in  boolean;
      IReady      : in  std_logic;
      Buffer_Addr : in  std_logic_vector(0 to 3);
      Instr_Addr  : out std_logic_vector(0 to C_DATA_SIZE-1);

      Op1_Low : out std_logic_vector(0 to 1);
      Op2_Low : out std_logic_vector(0 to 1);

      -- Debug Signals
      Dbg_Inhibit_EX   : in  std_logic;
      Stop_Instr_Fetch : in  std_logic;
      Op1              : out std_logic_vector(0 to C_DATA_SIZE-1);
      PC_OF            : out std_logic_vector(0 to C_DATA_SIZE-1);

      -- PVR signals
      MEM_PVR_Select  : in std_logic_vector(0 to 3);
      MEM_Sel_SPR_PVR : in boolean;

      -- Trace signals
      PC_EX         : out std_logic_vector(0 to C_DATA_SIZE-1);
      MSR           : out MSR_REG_TYPE;
      New_Reg_Value : out std_logic_vector(0 to C_DATA_SIZE-1);

      -- FSL Links signal
      FSL_Get_No            : out natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
      FSL_Get_Data          : in  std_logic_vector(0 to C_DATA_SIZE-1);  -- Data that is received
      EX_FSL_Control_Error  : in  std_logic;  -- A FSL Get control bit mismatch has occured
      FSL_Put_No            : out natural range 0 to C_MAX_FSL_LINKS-1;  -- Which FSL to operate on
      FSL_Put_Data          : out std_logic_vector(0 to C_DATA_SIZE-1);  -- Data that is received
      EX_FSL_Write_Carry    : in  std_logic;
      EX_FSL_Carry          : in  std_logic;

      -- Div Unit signals
      Start_Div   : in  std_logic;
      Not_Div_Op  : in  std_logic;
      Div_Done    : out std_logic;
      Div_By_Zero : out std_logic;

      -- FPU signals
      FPU_Op     : in  std_logic_vector(0 to 2);
      FPU_Cond   : in  std_logic_vector(0 to 2);
      Start_FPU  : in  std_logic;
      Not_FPU_Op : in  std_logic;
      FPU_Done   : out std_logic;
      FPU_Excep  : out std_logic;
      FSR_Write  : in  boolean;

      -- Instruction Cache signal
      ICache_Enabled : out boolean;
      DCache_Enabled : out boolean);
  end component Data_Flow;

  component Byte_Doublet_Handle is
    generic (
      C_TARGET    : TARGET_FAMILY_TYPE;
      C_OPB_WIDTH : natural range 4 to 64 := 32;
      C_DATA_SIZE : natural range 4 to 64);
    port (
      Clk               : in  std_logic;
      -- Reset             : in  boolean;
      Byte              : in  boolean;
      Doublet           : in  boolean;
      Op1_Low           : in  std_logic_vector(0 to 1);
      Op2_Low           : in  std_logic_vector(0 to 1);
      Data_Read         : in  std_logic_vector(0 to C_OPB_WIDTH-1);
      Data_Write        : in  std_logic_vector(0 to C_DATA_SIZE-1);
      Extend_Data_Write : out std_logic_vector(0 to C_OPB_WIDTH-1);
      Extend_Data_Read  : out std_logic_vector(0 to C_DATA_SIZE-1);
      Byte_Enable       : out std_logic_vector(0 to (C_OPB_WIDTH-1)/8);
      Low_Addr_Out      : out std_logic_vector(0 to 1));
  end component Byte_Doublet_Handle;
  
  component Debug is
    generic (
      C_USE_BARREL            : integer                   := 1;
      C_USE_DIV               : integer                   := 1;
      C_USE_HW_MUL            : integer                   := 1;
      C_USE_FPU               : integer                   := 0;
      C_USE_MSR_INSTR         : integer                   := 0;
      C_USE_PCMP_INSTR        : integer                   := 0;
      C_UNALIGNED_EXCEPTIONS  : integer                   := 0;
      C_ILL_OPCODE_EXCEPTION  : integer                   := 0;
      C_IOPB_BUS_EXCEPTION    : integer                   := 0;
      C_DOPB_BUS_EXCEPTION    : integer                   := 0;
      C_IPLB_BUS_EXCEPTION    : integer                   := 0;
      C_DPLB_BUS_EXCEPTION    : integer                   := 0;
      C_DIV_ZERO_EXCEPTION    : integer                   := 0;
      C_FPU_EXCEPTION         : integer                   := 0;
      C_FSL_EXCEPTION         : integer                   := 0;
      C_USE_EXTENDED_FSL_INSTR  : integer;
      C_FSL_LINKS             : integer                   := 1;
      C_PVR                   : integer                   := 0;
      C_PVR_USER1             : std_logic_vector(0 to 7);
      C_PVR_USER2             : std_logic_vector(0 to 31);
      C_MB_VERSION            : std_logic_vector(0 to 7);
      C_INTERCONNECT          : integer                   := 0;
      C_USE_ICACHE            : integer                   := 0;
      C_ICACHE_USE_FSL        : integer                   := 0;
      C_ICACHE_BASEADDR       : std_logic_vector(0 to 31) := X"00000000";
      C_ICACHE_HIGHADDR       : std_logic_vector(0 to 31) := X"3FFFFFFF";
      C_USE_DCACHE            : integer                   := 0;
      C_DCACHE_USE_FSL        : integer                   := 0;
      C_DCACHE_BASEADDR       : std_logic_vector(0 to 31) := X"00000000";
      C_DCACHE_HIGHADDR       : std_logic_vector(0 to 31) := X"3FFFFFFF";
      C_TARGET                : TARGET_FAMILY_TYPE;
      C_DATA_SIZE             : natural                   := 32;
      C_NUMBER_OF_PC_BRK      : natural range 0 to 15     := 1;
      C_NUMBER_OF_RD_ADDR_BRK : natural range 0 to 7      := 0;
      C_NUMBER_OF_WR_ADDR_BRK : natural range 0 to 7      := 0
      );
    port (
      -- JTAG_UART signals
      TClk    : in  std_logic;
      TDI     : in  std_logic;
      TDO     : out std_logic;
      Reg_En  : in  std_logic_vector(0 to 4);
      Shift   : in  std_logic;
      Capture : in  std_logic;          -- Read
      Update  : in  std_logic;          -- Write

      -- MicroBlaze signals
      Clk      : in std_logic;
      Reset    : in boolean;
      Dbg_Stop : in std_logic;

      -- Needed for the Breakpoint
      PC_OF      : in std_logic_vector(0 to C_DATA_SIZE-1);
      OF_PipeRun : in boolean;

      Use_Imm_Reg       : in  boolean;
      Branch_with_delay : in  boolean;
      Delay_Slot_Instr  : out std_logic;

      -- Registers to read
      PC_EX       : in std_logic_vector(0 to C_DATA_SIZE-1);
      Valid_Instr : in std_logic;
      MSR         : in MSR_REG_TYPE;

      -- Signals needed for Read/Write to memory
      Reg_Write     : in std_logic;
      New_Reg_Value : in std_logic_vector(0 to C_DATA_SIZE-1);

      Debug_Ready      : out std_logic;
      Instr_Debug      : out std_logic_vector(0 to 31);
      Stop_Instr_Fetch : out std_logic;

      -- Signals needed for Memory breakpoints
      Data_Addr   : in std_logic_vector(0 to C_DATA_SIZE-1);
      Data_Write  : in std_logic_vector(0 to C_DATA_SIZE-1);
      Write_Instr : in std_logic;
      Read_Instr  : in std_logic;
      DReady      : in std_logic;

      -- MicroBlaze stalling conditions
      FSL_Stalled    : in std_logic;
      Memory_Stalled : in std_logic;

      -- Stop MicroBlaze
      Ok_To_Stop            : in  std_logic;  -- Ok to stop the CPU ie. No BRK or
      -- Interrupts and a valid instruction
      -- in OF stage
      Dbg_Inhibit_EX        : out std_logic;
      Stop_CPU              : out std_logic;
      Dbg_Disable_Interrupt : out boolean;
      MB_Halted             : out std_logic;

      -- Debug signals for debugging debug logic!!!!
      Control_Reg_D : out std_logic_vector(0 to 3);
      Command_Reg_D : out std_logic_vector(0 to 7)

      );
  end component Debug;

  component FSL_Module is
    generic (
      C_TARGET               : TARGET_FAMILY_TYPE;
      C_AREA_OPTIMIZED       : integer;
      C_FSL_LINKS            : integer;
      C_USE_EXTENDED_FSL_INSTR  : integer;
      C_MAX_FSL_LINKS        : natural;
      C_DATA_SIZE            : integer;
      C_FSL_DATA_SIZE        : integer
    );
    port (
      -- General
      Clk                  : in  std_logic;
      Reset                : in  std_logic;
      
      -- FSL Pipe control
      EX_PipeRun           : in  boolean;
      FSL_Stall            : out std_logic; -- A blocking FSL instruction is stalling pipeline
      
      -- FSL In Link
      FSL_S_Read           : out std_logic_vector(0 to C_MAX_FSL_LINKS-1);
      FSL_S_Data           : in  std_logic_vector(0 to C_MAX_FSL_LINKS*C_FSL_DATA_SIZE-1);
      FSL_S_Control        : in  std_logic_vector(0 to C_MAX_FSL_LINKS-1);
      FSL_S_Exists         : in  std_logic_vector(0 to C_MAX_FSL_LINKS-1);
      
      -- FSL Out Links
      FSL_M_Write          : out std_logic_vector(0 to C_MAX_FSL_LINKS-1);
      FSL_M_Control        : out std_logic_vector(0 to C_MAX_FSL_LINKS-1);
      FSL_M_Data           : out std_logic_vector(0 to C_MAX_FSL_LINKS * C_FSL_DATA_SIZE-1);
      FSL_M_Full           : in  std_logic_vector(0 to C_MAX_FSL_LINKS-1);
      
      --