microblaze.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      C_DATA_SIZE            : natural range 1 to 64;
      C_DEBUG_ENABLED        : integer;
      C_TARGET               : TARGET_FAMILY_TYPE;
      C_PVR                  : integer;
      C_USE_ICACHE           : integer;
      C_ALLOW_ICACHE_WR      : integer;
      C_USE_DCACHE           : integer;
      C_ALLOW_DCACHE_WR      : integer;
      C_USE_BARREL           : integer;
      C_USE_MSR_INSTR        : integer;
      C_USE_DIV              : integer;
      C_USE_FPU              : integer;
      C_FSL_LINKS            : integer;
      C_USE_EXTENDED_FSL_INSTR  : integer;
      C_UNALIGNED_EXCEPTIONS : integer;
      C_ILL_OPCODE_EXCEPTION : integer;
      C_DETECT_OPCODE_0x0    : boolean;
      C_IOPB_BUS_EXCEPTION   : integer;
      C_DOPB_BUS_EXCEPTION   : integer;
      C_IPLB_BUS_EXCEPTION   : integer;
      C_DPLB_BUS_EXCEPTION   : integer;
      C_DIV_ZERO_EXCEPTION   : integer;
      C_FPU_EXCEPTION        : integer;
      C_FSL_EXCEPTION        : integer;
      C_USE_MUL_INSTR        : boolean;
      C_USE_MUL64            : boolean;
      C_USE_PCMP_INSTR       : boolean
      );
    port (
      Clk   : in std_logic;
      Reset : in boolean;

      -- Interrupt handling
      Ext_BRK    : in std_logic;
      Ext_NM_BRK : in std_logic;
      Interrupt  : in boolean;

      -- Instruction bus control
      IFetch      : out std_logic;
      I_AS        : out std_logic;
      IReady      : in  std_logic;
      Instr       : in  std_logic_vector(0 to 31);
      I_Exception : in  std_logic;

      --  Data bus control
      D_AS                    : out std_logic;
      Read_Strobe             : out std_logic;
      Write_Strobe            : out std_logic;
      Read_Strobe_No_Dbg      : out std_logic;
      Write_Strobe_No_Dbg     : out std_logic;
      Mem_Strobe              : out std_logic;
      DReady                  : in  std_logic;
      D_Exception             : in  std_logic;
      Doublet_Read            : out boolean;
      Quadlet_Read            : out boolean;
      Byte                    : out boolean;
      Doublet                 : out boolean;
      word_r1_r2_unalignment  : in  std_logic;
      word_r1_imm_unalignment : in  std_logic;
      halfword_unalignment    : in  std_logic;

      -- Pipeline control
      OF_PipeRun : out boolean;

      -- Register File signals
      Write_Addr    : out std_logic_vector(0 to 4);
      Reg1_Addr     : out std_logic_vector(0 to 4);
      Reg2_Addr     : out std_logic_vector(0 to 4);
      Reg_Write     : out boolean;
      Reg_Write_Dbg : out boolean;

      -- Operand select control signals
      Take_Interrupt : out rboolean;
      Take_Exception : out rboolean;
      Take_Ext_BRK   : out rboolean;
      Store_PC_For_Intr      : out rboolean;
      Store_PC_For_Intr_NoImm: out rboolean;
      OpSel1_PC      : out rboolean;
      OpSel1_SPR     : out rboolean;
      -- OpSel1_FSR     : out rboolean;
      OpSel2_Imm     : out rboolean;
      Res_Forward1   : out rboolean;
      Res_Forward2   : out rboolean;
      Imm_Instr      : out boolean;
      Use_Imm_Reg    : out boolean;
      Imm_Value      : out std_logic_vector(0 to 15);
      MFS_Reg_Sel    : out std_logic_vector(0 to 2);

      -- Arith control signals
      Carry_In      : out std_logic;
      Compare_Instr : out std_logic;
      Unsigned_Op   : out std_logic;
      ALU_Op        : out std_logic_vector(0 to 1);
      ALU_Carry     : in  std_logic;

      -- Shift Control
      Shift_Carry_Out : in  std_logic;
      Sext8           : out boolean;
      Sext16          : out boolean;
      Sign_Extend     : out boolean;
      Shift_Oper      : out std_logic_vector(0 to 1);
      Shift_Carry_In  : out std_logic;

      -- Logic Control
      Logic_Oper   : out std_logic_vector(0 to 1);
      Select_Logic : out boolean;

      -- Extra Instructions
      PCMP_Instr : out rboolean;

      -- Mul Control
      EX_Not_Mul_Op   : out boolean;
      EX_Mulh_Instr   : out boolean;
      EX_Mulhu_Instr  : out boolean;
      EX_Mulhsu_Instr : out boolean;

      -- Result mux control signals
      Result_Sel : out std_logic_vector(0 to 1);

      -- Barrel Shifter control signals
      Arith_Shift   : out std_logic;
      Left_Shift    : out std_logic;
      Not_Barrel_Op : out std_logic;

      -- MSR signals
      New_Carry          : out std_logic;
      Write_Carry        : out rboolean;
      MTSMSR_Write       : out boolean;
      Disable_Interrupts : out rboolean;
      Enable_Interrupts  : out rboolean;
      Set_BIP            : out rboolean;
      Reset_BIP          : out rboolean;
      BIP_Active         : in  boolean;
      Carry              : in  std_logic;
      Enable_Interrupt   : in  boolean;
      Enable_BusLock     : in  boolean;
      Write_ICache       : out boolean;
      Write_DCache       : out boolean;
      ICache_Read_Idle   : in  boolean;
      DCache_Read_Idle   : in  boolean;
      MSRxxx_Instr       : out rboolean;
      MSRclr_Instr       : out rboolean;

      -- Branch signals
      Reg_Test_Equal   : out std_logic;
      Reg_Test_Equal_N : out std_logic;
      Reg_Zero         : in  std_logic;
      Reg_neg          : in  std_logic;

      -- Select which PVR to read
      MEM_PVR_Select  : out  std_logic_vector(0 to 3);
      MEM_Sel_SPR_PVR : out  boolean;

      -- PC module signals
      Valid_Fetch : out std_logic;
      PC_Incr     : out boolean;
      Jump        : out rboolean;
      PC_Write    : out boolean;
      Buffer_Addr : out std_logic_vector(0 to 3);

      -- Trace and debug signals
      Stop_CPU              : in  std_logic;
      Dbg_Inhibit_EX        : in  std_logic;
      Dbg_Want_To_Break_FSL : in  std_logic;
      FSL_Will_Dbg_Break    : out std_logic;
      Ok_To_Stop            : out std_logic;
      Stop_Instr_Fetch      : in  std_logic;
      Branch_with_delay     : out boolean;
      ESR                   : in  ESR_TYPE;
      Exception_Taken       : out std_logic;
      Exception_Kind        : out EXCEPTION_KIND_TYPE;

      Valid_Instr           : out std_logic;
      Trace_Valid_Instr     : out std_logic;
      Interrupt_Taken       : out std_logic;
      Branch_Instr          : out std_logic;
      Instr_EX              : out std_logic_vector(0 to 31);
      Load_Store_Instr_Addr : out std_logic;
      Use_Store_Instr_Addr  : out std_logic;

      -- Exception information bits
      Load_EAR                 : out rboolean;
      Load_EDR                 : out rboolean;
      Load_ESR                 : out rboolean;
      SW_Instr                 : out std_logic;
      Word_Access              : out std_logic;
      Unaligned_Exception      : out std_logic;
      Illegal_Opcode_Exception : out std_logic;
      IExt_Bus_Exception       : out std_logic;
      DExt_Bus_Exception       : out std_logic;
      Div_Zero_Exception       : out std_logic;
      FPU_Exception            : out std_logic;
      FSL_Exception            : out std_logic;
      EX_delayslot_Instr       : out boolean;

      -- Exception Control bits
      Clr_ESR            : out rboolean;
      Disable_Exceptions : out rboolean;
      Enable_Exceptions  : out rboolean;
      Exceptions_Enabled : in  boolean;
      Set_EIP            : out rboolean;
      Reset_EIP          : out rboolean;
      EIP_Active         : in  boolean;
      EX_Load_BTR        : out boolean;

      -- Div Unit signals
      Start_Div   : out std_logic;
      Not_Div_Op  : out std_logic;
      Div_Done    : in  std_logic;
      Div_By_Zero : in  std_logic;

      -- FPU signals
      FPU_Op     : out std_logic_vector(0 to 2);
      FPU_Cond   : out std_logic_vector(0 to 2);
      Start_FPU  : out std_logic;
      Not_FPU_Op : out std_logic;
      FPU_Done   : in  std_logic;
      FPU_Excep  : in  std_logic;
      FSR_Write  : out boolean;

      -- FSL Pipe control
      FSL_Stall             : in  std_logic;  -- A blocking FSL instruction is stalling pipeline
      
      -- Get signals
      FSL_Get               : out std_logic;  -- A FSL get instruction
      FSL_Get_Test          : out std_logic;  -- This is a test instruction.
      FSL_Get_Inhibit       : out std_logic;  -- FSL Get must not execute (exceptions, ....)
      FSL_Get_Control       : out std_logic;  -- The get control bit from the FSL instruction
      FSL_Get_Blocking      : out std_logic;  -- The FSL get instruction is blocking
      FSL_Get_Break         : out std_logic;  -- The FSL is breaked
      FSL_Get_Succesful     : in  std_logic;  -- The FSL get was succesful
      EX_FSL_Control_Error  : in  std_logic;  -- A FSL Get control bit mismatch has occured
      
      -- Put signals
      FSL_Put               : out std_logic;  -- A FSL put instruction
      FSL_Put_Test          : out std_logic;  -- This is a test instruction.
      FSL_Put_Inhibit       : out std_logic;  -- FSL Put must not execute (exceptions, ....)
      FSL_Put_Control       : out std_logic;  -- The put control bit from the FSL instruction
      FSL_Put_Blocking      : out std_logic;  -- The FSL get instruction is blocking
      FSL_Put_Break         : out std_logic;  -- The FSL is breaked
      FSL_Put_Succesful     : in  std_logic;  -- The FSL put was succesful
      
      -- Carry & result
      Not_MB_Get_Op         : out std_logic;
      EX_MSR_Load_FSL_C     : out std_logic;
      EX_FSL_Write_Carry    : in  std_logic;
      EX_FSL_Carry          : in  std_logic
    );
  end component Decode;

  component Data_Flow is
    generic (

      -- global generics
      C_DATA_SIZE : natural range 4 to 64;
      C_TARGET    : TARGET_FAMILY_TYPE;
      C_AREA_OPTIMIZED       : integer                := 0;

      -- generics for "Operand_Select_I"
      C_PC_START_ADDR  : string;
      C_EXCEPTION_ADDR : string;
      C_INTERRUPT_ADDR : string;
      C_EXT_BRK_ADDR   : string;

      C_USE_EXCEPTIONS : boolean;

      -- generics for using Barrel Shifter
      C_USE_BARREL : integer;

      C_USE_DIV : integer;

      -- generic for using hardware multiplier
      C_USE_HW_MUL : boolean;
      C_USE_MUL64  : boolean;
      
      -- generic for using FPU
      C_USE_FPU : integer;

      -- generic for using PCMP instructions
      C_USE_PCMP_INSTR : boolean := true;

      -- generic for enabling msrxxx instructions
      C_USE_MSR_INSTR : integer;

      C_BUFFER_SIZE   : natural range 1 to 16;
      C_DEBUG_ENABLED : integer;

      C_FSL_LINKS               : integer;
      C_USE_EXTENDED_FSL_INSTR  : integer;
      C_MAX_FSL_LINKS           : natural;

      -- generics used by PVR
      C_PVR                   : integer;   -- Which PVR mode None=0, Basic=1, Full=2
      C_MB_VERSION            : std_logic_vector(0 to 7);
      C_PVR_USER1             : std_logic_vector(0 to 7);
      C_PVR_USER2             : std_logic_vector(0 to 31);
      C_INTERCONNECT          : integer;
      C_D_OPB                 : integer;
      C_D_PLB                 : integer;
      C_D_LMB                 : integer;
      C_I_OPB                 : integer;
      C_I_PLB                 : integer;
      C_I_LMB                 : integer;
      C_INTERRUPT_IS_EDGE     : integer;
      C_EDGE_IS_POSITIVE      : integer;
      C_OPCODE_0x0_ILLEGAL    : integer;
      C_UNALIGNED_EXCEPTIONS  : integer;
      C_ILL_OPCODE_EXCEPTION  : integer;
      C_IOPB_BUS_EXCEPTION    : integer;
      C_DOPB_BUS_EXCEPTION    : integer;
      C_IPLB_BUS_EXCEPTION    : integer;
      C_DPLB_BUS_EXCEPTION    : integer;
      C_DIV_ZERO_EXCEPTION    : integer;
      C_FPU_EXCEPTION         : integer;
      C_FSL_EXCEPTION         : integer;
      C_NUMBER_OF_PC_BRK      : integer;
      C_NUMBER_OF_RD_ADDR_BRK : integer;
      C_NUMBER_OF_WR_ADDR_BRK : integer;
      C_USE_ICACHE            : integer;
      C_ADDR_TAG_BITS         : integer;
      C_ICACHE_USE_FSL        : integer;
      C_ALLOW_ICACHE_WR       : integer;
      C_ICACHE_LINE_LEN       : integer;
      C_CACHE_BYTE_SIZE       : integer;
      C_ICACHE_ALWAYS_USED    : integer;
      C_USE_DCACHE            : integer;